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TPS51916

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DDR2/3/3L/4 Memory Power Solution Synchronous Buck Controller

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Data sheet

TPS51916

ACTIVE
Data sheet Order now

Product details

Vin (min) (V) 3 Vin (max) (V) 28 Vout (min) (V) 0.7 Vout (max) (V) 1.8 Features Complete Solution, Eco Mode, S3/S5 Support Rating Catalog Operating temperature range (°C) -40 to 85 Iq (typ) (mA) 0.6 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
Vin (min) (V) 3 Vin (max) (V) 28 Vout (min) (V) 0.7 Vout (max) (V) 1.8 Features Complete Solution, Eco Mode, S3/S5 Support Rating Catalog Operating temperature range (°C) -40 to 85 Iq (typ) (mA) 0.6 Product type DDR DDR memory type DDR, DDR2, DDR3, DDR3L, DDR4, LPDDR2, LPDDR3
WQFN (RUK) 20 9 mm² 3 x 3
  • Synchronous Buck Controller (VDDQ)
    • Conversion Voltage Range: 3 V to 28 V
    • Output Voltage Range: 0.7 V to 1.8 V
    • 0.8% VREF Accuracy
    • Selectable Control Architecture
      • D-CAP™ Mode for Fast Transient Response
      • D-CAP2™ Mode for Ceramic Output Capacitors
    • Selectable 300 kHz, 400 kHz, 500 kHz, or 670 kHz Switching Frequencies
    • Optimized Efficiency at Light and Heavy Loads with Auto-skip Function
    • Supports Soft-Off in S4 and S5 States
    • OCL/OVP/UVP/UVLO Protections
    • Powergood Output
  • 2-A LDO(VTT), Buffered Reference(VTTREF)
    • 2-A (Peak) Sink and Source Current
    • Buffered, Low Noise, 10-mA VTTREF Output
    • 0.8% VTTREF, 20-mV VTT Accuracy
    • Supports High-Z (S3) and Soft-Off (S4, S5)
  • Thermal Shutdown
  • 20-Pin, 3 mm × 3 mm, QFN Package
  • Create a WEBENCH Design
  • Synchronous Buck Controller (VDDQ)
    • Conversion Voltage Range: 3 V to 28 V
    • Output Voltage Range: 0.7 V to 1.8 V
    • 0.8% VREF Accuracy
    • Selectable Control Architecture
      • D-CAP™ Mode for Fast Transient Response
      • D-CAP2™ Mode for Ceramic Output Capacitors
    • Selectable 300 kHz, 400 kHz, 500 kHz, or 670 kHz Switching Frequencies
    • Optimized Efficiency at Light and Heavy Loads with Auto-skip Function
    • Supports Soft-Off in S4 and S5 States
    • OCL/OVP/UVP/UVLO Protections
    • Powergood Output
  • 2-A LDO(VTT), Buffered Reference(VTTREF)
    • 2-A (Peak) Sink and Source Current
    • Buffered, Low Noise, 10-mA VTTREF Output
    • 0.8% VTTREF, 20-mV VTT Accuracy
    • Supports High-Z (S3) and Soft-Off (S4, S5)
  • Thermal Shutdown
  • 20-Pin, 3 mm × 3 mm, QFN Package
  • Create a WEBENCH Design

The TPS51916 device provides a complete power supply for DDR2, DDR3, DDR3L, and DDR4 memory systems in the lowest total cost and minimum space. It integrates a synchronous buck regulator controller (VDDQ) with a 2-A sink and 2-A source tracking LDO (VTT) and buffered low noise reference (VTTREF).

The device employs D-CAP™ mode coupled with 300 kHz or 400 kHz frequencies for ease-of-use and fast transient response or D-CAP2™ mode coupled with higher 500 kHz or 670 kHz frequencies to support ceramic output capacitor without an external compensation circuit. The VTTREF tracks VDDQ/2 within excellent 0.8% accuracy. The VTT, which provides 2-A sink and 2-A source peak current capabilities, requires only 10-µF of ceramic capacitance. A dedicated LDO supply input is available.

The device also provides excellent power supply performance. It supports flexible power state control, placing VTT at high-Z in S3 and discharging VDDQ, VTT and VTTREF (soft-off) in S4 or S5 state. Programmable OCL with low-side MOSFET RDS(on) sensing, OVP, UVP, UVLO and thermal shutdown protections are also available.

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The TPS51916 device provides a complete power supply for DDR2, DDR3, DDR3L, and DDR4 memory systems in the lowest total cost and minimum space. It integrates a synchronous buck regulator controller (VDDQ) with a 2-A sink and 2-A source tracking LDO (VTT) and buffered low noise reference (VTTREF).

The device employs D-CAP™ mode coupled with 300 kHz or 400 kHz frequencies for ease-of-use and fast transient response or D-CAP2™ mode coupled with higher 500 kHz or 670 kHz frequencies to support ceramic output capacitor without an external compensation circuit. The VTTREF tracks VDDQ/2 within excellent 0.8% accuracy. The VTT, which provides 2-A sink and 2-A source peak current capabilities, requires only 10-µF of ceramic capacitance. A dedicated LDO supply input is available.

The device also provides excellent power supply performance. It supports flexible power state control, placing VTT at high-Z in S3 and discharging VDDQ, VTT and VTTREF (soft-off) in S4 or S5 state. Programmable OCL with low-side MOSFET RDS(on) sensing, OVP, UVP, UVLO and thermal shutdown protections are also available.

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Technical documentation

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Type Title Date
* Data sheet TPS51916 Complete DDR2, DDR3, DDR3L and DDR4 Memory Power Solution Synchronous Buck Controller, 2-A LDO, Buffered Reference datasheet (Rev. F) PDF | HTML 19 Dec 2018
Selection guide Power Management Guide 2018 (Rev. R) 25 Jun 2018
More literature Computing DDR DC-DC Power Solutions 22 Aug 2012
User guide TPS51916EVM-746 User's Guide 19 Aug 2011

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

TPS51916EVM-746 — Evaluation Module for TPS51916 DDR2, DDR3 & DDR3L Memory Power Solution Synchronous Buck Controller

The TPS51916EVM-746 evaluation module is a fully assembled and tested circuit for evaluating the TPS51916 low-dropout (LDO) regulator. The TPS51916 provides a complete power supply for DDR2, DDR3, DDR3L and DDR4 memory system in the lowest total cost and minimum space. The TPS51916 integrates a (...)
User guide: PDF
Not available on TI.com
Simulation model

TPS51916 PSpice Transient Model

SLUM206.ZIP (80 KB) - PSpice Model
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Simulation model

TPS51916 TINA-TI Transient Reference Design

SLUM265.TSC (253 KB) - TINA-TI Reference Design
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Simulation model

TPS51916 TINA-TI Transient Spice Model

SLUM266.ZIP (78 KB) - TINA-TI Spice Model
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Reference designs

TIDA-00020 — Intel IMVP7 2nd Generation Core Mobile (Core i7) Power Management Reference Design

The Intel® Core i7 power management design is a reference design for the Intel® IMVP-7 Serial VID (SVID) power system. This design features an IMVP-7 3-phase CPU supply, a single-phase GPU Vcore supply, a 1.05-VCC IO supply, and a DDR3L/DDR4 memory rail. To greatly improve power (...)
Test report: PDF
Schematic: PDF
Package Pins CAD symbols, footprints & 3D models
WQFN (RUK) 20 Ultra Librarian
TI's Standard Terms and Conditions for Evaluation Items apply.

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