The TPSI2072-Q1 is a two channel isolated solid
state relay designed for high voltage automotive and industrial applications. The
TPSI2072-Q1 uses TIs high reliability capacitive
isolation technology in combination with internal back-to-back MOSFETs to form a
completely integrated solution requiring no secondary side power supply. The TPSI2072-Q1 improves system reliability as TIs
capacitive isolation technology does not suffer from mechanical wearout or photo
degradation failure modes common in mechanical relay and photo relay components.
The primary side of the device is
powered by only 9 mA of input current and incorporates fail-safe EN1 and EN2 pins preventing any
possibility of back powering the VDD supply. In most applications, the VDD pin of
the device should be connected to a system supply between 4.5 V–20 V and the EN1 and EN2 pins of the device should be
driven by a GPIO output with logic HI between 2.1 V–20 V. In other applications, the
VDD, EN1, and EN2 pins could be driven
together directly from the system supply or from a GPIO output.
Each channel on the secondary side consists
of back-to-back MOSFETs with a standoff voltage of +/-600 V from SM to S1 and SM to S2. The TPSI2072-Q1 MOSFETs avalanche robustness and thermally
conscious package design allow it to robustly support system level dielectric
withstand testing (HiPot) and DC fast charger surge currents of up to 2 mA without
requiring any external components.
The TPSI2072-Q1 is a two channel isolated solid
state relay designed for high voltage automotive and industrial applications. The
TPSI2072-Q1 uses TIs high reliability capacitive
isolation technology in combination with internal back-to-back MOSFETs to form a
completely integrated solution requiring no secondary side power supply. The TPSI2072-Q1 improves system reliability as TIs
capacitive isolation technology does not suffer from mechanical wearout or photo
degradation failure modes common in mechanical relay and photo relay components.
The primary side of the device is
powered by only 9 mA of input current and incorporates fail-safe EN1 and EN2 pins preventing any
possibility of back powering the VDD supply. In most applications, the VDD pin of
the device should be connected to a system supply between 4.5 V–20 V and the EN1 and EN2 pins of the device should be
driven by a GPIO output with logic HI between 2.1 V–20 V. In other applications, the
VDD, EN1, and EN2 pins could be driven
together directly from the system supply or from a GPIO output.
Each channel on the secondary side consists
of back-to-back MOSFETs with a standoff voltage of +/-600 V from SM to S1 and SM to S2. The TPSI2072-Q1 MOSFETs avalanche robustness and thermally
conscious package design allow it to robustly support system level dielectric
withstand testing (HiPot) and DC fast charger surge currents of up to 2 mA without
requiring any external components.