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DP83865

不推荐用于新设计

千兆位 10/100/1000 PHYTER V 以太网物理层收发器

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DP83865 不推荐用于新设计
该产品会持续为现有客户提供。新设计应考虑替代产品。
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功能与比较器件相似
DP83867E 正在供货 具有 SGMII 接口、支持工作温度范围的耐用型低延迟千兆位以太网 PHY 收发器 The DP83867E requires less than half the power of the DP83865 and has higher temperature range.

DP83865

不推荐用于新设计
数据表 立即订购

产品详情

Datarate (Mbps) 10/100/1000 Interface type GMII, MII, RGMII Number of ports Single Rating Catalog Supply voltage (V) 1.8 Operating temperature range (°C) 0 to 70 Number of LEDs 5 ESD HBM (kV) 6
Datarate (Mbps) 10/100/1000 Interface type GMII, MII, RGMII Number of ports Single Rating Catalog Supply voltage (V) 1.8 Operating temperature range (°C) 0 to 70 Number of LEDs 5 ESD HBM (kV) 6
QFP (NND) 128 399.04 mm² 23.2 x 17.2
  • Ultra low power consumption typically 1.1 watt
  • Fully compliant with IEEE 802.3 10BASE-T, 100BASE-TX and 1000BASE-T specifications
  • Integrated PMD sublayer featuring adaptive equalization and baseline wander compensation according to ANSI X3.T12
  • 3.3V or 2.5V MAC interfaces:
  • IEEE 802.3u MII
  • IEEE 802.3z GMII
  • RGMII version 1.3
  • User programmable GMII pin ordering
  • IEEE 802.3u Auto-Negotiation and Parallel Detection
  • Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s, and 10 Mb/s full duplex and half duplex devices
  • Speed Fallback mode to achieve quality link
  • Cable length estimator
  • LED support for activity, full / half duplex, link1000, link100 and link10, user programmable (manual on/off), or reduced LED mode
  • Supports 25 MHz operation with crystal or oscillator.
  • Requires only two power supplies, 1.8V (core and analog) and 2.5V (analog and I/O). 3.3V is supported as an alternative supply for I/O voltage
  • User programable interrupt
  • Supports Auto-MDIX at 10, 100 and 1000 Mb/s
  • Supports JTAG (IEEE1149.1)
  • 128-pin PQFP package (14mm x 20mm)
  • Ultra low power consumption typically 1.1 watt
  • Fully compliant with IEEE 802.3 10BASE-T, 100BASE-TX and 1000BASE-T specifications
  • Integrated PMD sublayer featuring adaptive equalization and baseline wander compensation according to ANSI X3.T12
  • 3.3V or 2.5V MAC interfaces:
  • IEEE 802.3u MII
  • IEEE 802.3z GMII
  • RGMII version 1.3
  • User programmable GMII pin ordering
  • IEEE 802.3u Auto-Negotiation and Parallel Detection
  • Fully Auto-Negotiates between 1000 Mb/s, 100 Mb/s, and 10 Mb/s full duplex and half duplex devices
  • Speed Fallback mode to achieve quality link
  • Cable length estimator
  • LED support for activity, full / half duplex, link1000, link100 and link10, user programmable (manual on/off), or reduced LED mode
  • Supports 25 MHz operation with crystal or oscillator.
  • Requires only two power supplies, 1.8V (core and analog) and 2.5V (analog and I/O). 3.3V is supported as an alternative supply for I/O voltage
  • User programable interrupt
  • Supports Auto-MDIX at 10, 100 and 1000 Mb/s
  • Supports JTAG (IEEE1149.1)
  • 128-pin PQFP package (14mm x 20mm)

The DP83865 is a fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols.

The DP83865 is an ultra low power version of the DP83861 and DP83891. It uses advanced 0.18 um, 1.8 V CMOS technology, fabricated at National Semiconductors South Portland, Maine facility.

The DP83865 is designed for easy implementation of 10/100/1000 Mb/s Ethernet LANs. It interfaces directly to Twisted Pair media via an external transformer. This device interfaces directly to the MAC layer through the IEEE 802.3u Standard Media Independent Interface (MII), the IEEE 802.3z Gigabit Media Independent Interface (GMII), or Reduced GMII (RGMII).

The DP83865 is a fourth generation Gigabit PHY with field proven architecture and performance. Its robust performance ensures drop-in replacement of existing 10/100 Mbps equipment with ten to one hundred times the performance using the existing networking infrastructure.

The DP83865 is a fully featured Physical Layer transceiver with integrated PMD sublayers to support 10BASE-T, 100BASE-TX and 1000BASE-T Ethernet protocols.

The DP83865 is an ultra low power version of the DP83861 and DP83891. It uses advanced 0.18 um, 1.8 V CMOS technology, fabricated at National Semiconductors South Portland, Maine facility.

The DP83865 is designed for easy implementation of 10/100/1000 Mb/s Ethernet LANs. It interfaces directly to Twisted Pair media via an external transformer. This device interfaces directly to the MAC layer through the IEEE 802.3u Standard Media Independent Interface (MII), the IEEE 802.3z Gigabit Media Independent Interface (GMII), or Reduced GMII (RGMII).

The DP83865 is a fourth generation Gigabit PHY with field proven architecture and performance. Its robust performance ensures drop-in replacement of existing 10/100 Mbps equipment with ten to one hundred times the performance using the existing networking infrastructure.
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类型 标题 下载最新的英语版本 日期
* 数据表 DP83865 Gig PHYTER V 10/100/1000 Ethernet Physical Layer 数据表 (Rev. B) 2007年 12月 11日

订购和质量

包含信息：
  • RoHS
  • REACH
  • 器件标识
  • 引脚镀层/焊球材料
  • MSL 等级/回流焊峰值温度
  • MTBF/时基故障估算
  • 材料成分
  • 鉴定摘要
  • 持续可靠性监测
包含信息：
  • 制造厂地点
  • 封装厂地点