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TPS53688

ACTIVE

Dual-channel, 8 phase step-down, digital multiphase D-CAP+™ controller with VR13.HC SVID and PMBus

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Data sheet

TPS53688

ACTIVE
Data sheet Order now

Product details

Vin (min) (V) 4.5 Vin (max) (V) 17 Iout (max) (A) 765 Operating temperature range (°C) -40 to 125 Control mode D-CAP+ Topology Multiphase Rating Catalog Vout (min) (V) 0.25 Vout (max) (V) 5.5 Features Adjustable current limit, Dynamic Voltage Scaling, Enable, Frequency synchronization, I2C, Light Load Efficiency, Multiple Outputs, PMBus, Phase Interleaving, Power good, Pre-Bias Start-Up, Remote Sense, SVID, Synchronous Rectification, UVLO adjustable, Voltage Margining Iq (typ) (µA) 50000 Number of phases 8
Vin (min) (V) 4.5 Vin (max) (V) 17 Iout (max) (A) 765 Operating temperature range (°C) -40 to 125 Control mode D-CAP+ Topology Multiphase Rating Catalog Vout (min) (V) 0.25 Vout (max) (V) 5.5 Features Adjustable current limit, Dynamic Voltage Scaling, Enable, Frequency synchronization, I2C, Light Load Efficiency, Multiple Outputs, PMBus, Phase Interleaving, Power good, Pre-Bias Start-Up, Remote Sense, SVID, Synchronous Rectification, UVLO adjustable, Voltage Margining Iq (typ) (µA) 50000 Number of phases 8
WQFN (RSB) 40 25 mm² 5 x 5
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* Data sheet TPS53688 Dual-Channel (N + M ≤ 8 phase) D-CAP+™ , Step-Down, Digital Multiphase datasheet (Rev. A) 15 Sep 2020

Design & development

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Simulation model

TPS53688 IBIS MODEL

SLUM683.ZIP (79 KB) - IBIS Model
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Reference designs

TIDA-010241 — Flexible power reference design for high performance Xilinx® and Intel® FPGA platforms

As the processing capabilities of field-programmable gate arrays (FPGAs) continue to increase, the number of power rails increase and the requirements per rail become more stringent. To manage these requirements, power management ICs (PMICs) and controllers are necessary to power all the rails and (...)
Design guide: PDF
Package Pins CAD symbols, footprints & 3D models
WQFN (RSB) 40 Ultra Librarian
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