The TPS7A83A is a low-noise (4.4 µVRMS), low-dropout, linear regulator (LDO) capable of sourcing 2 A with only 200 mV of maximum dropout. The TPS7A8300A output voltage is pin programmable from 0.8 V to 3.95 V with a 50-mV resolution, and adjustable from 0.8 V to 5.2 V using an external resistor divider. The TPS7A8301A output voltage is pin programmable from 0.5 V to 2.075 V with a 25-mV resolution, and adjustable from 0.5 V to 5.2 V using an external resistor divider.
The combination of low noise , high PSRR, and high output current capability makes the TPS7A83A an excellent choice to power noise-sensitive components such as those found in high-speed communications, video, medical, or test and measurement applications. This device is designed for powering high-performance serializer and deserializer (SerDes), analog-to-digital converters (ADCs), digital-to-analog converters (DACs), and RF components because the high performance of the TPS7A83A limits power-supply-generated phase noise and clock jitter. Specifically, RF amplifiers benefit from the high-performance and 5.2-V output capability of the device.
For digital loads [such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), and digital signal processors (DSPs)] requiring low-input voltage, low-output (LILO) voltage operation, the exceptional accuracy (0.75% over load and temperature), remote sensing, excellent transient performance, and soft-start capabilities of the TPS7A83A ensure optimal system performance.
The versatility of the TPS7A83A makes the device a component of choice for many demanding applications.
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | TPS7A83A 2-A, High-Accuracy (0.75%), Low-Noise (4.4 μVRMS) LDO Regulator datasheet (Rev. B) | PDF | HTML | 06 Oct 2021 |
| White paper | Demystifying LDO Turn-On (Start-Up) Time (Rev. B) | PDF | HTML | 10 Mar 2026 | |
| White paper | Reduce System Noise Using Parallel LDOs | PDF | HTML | 03 Nov 2025 | |
| White paper | Parallel LDO Architecture Design Using Ballast Resistors | PDF | HTML | 14 Dec 2022 | |
| White paper | Comprehensive Analysis and Universal Equations for Parallel LDO's Using Ballast | PDF | HTML | 13 Dec 2022 | |
| Selection guide | Low Dropout Regulators Quick Reference Guide (Rev. P) | 21 Mar 2018 |
For additional terms or required resources, click any title below to view the detail page where available.
The TPS7A8300EVM-579 evaluation module is designed for a typical configuration to evaluate the operation and performance of the TPS7A8300, 2-A low dropout voltage regulator for high speed communication systems.
The EVM circuit board is configured to be a reference design for engineering applications (...)
The parallel low-dropout (LDO) calculator is a Microsoft® Excel®-based tool that provides worst-case analysis for parallel LDO regulators using ballast resistors. The tool helps the user identify the minimum number of parallel LDO regulators required and optimum ballast resistance for a (...)
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VQFN (RGR) | 20 | Ultra Librarian |
| VQFN (RGW) | 20 | Ultra Librarian |
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Initial Release