The TPSI2260-Q1 is an isolated solid state relay designed for high voltage automotive and industrial applications. The TPSI2260-Q1 uses TIs high reliability reinforced capacitive isolation technology in combination with internal back-to-back MOSFETs to form a completely integrated solution requiring no secondary side power supply. The TPSI2260-Q1 improves system reliability as TIs capacitive isolation technology does not suffer from mechanical wearout or photo degradation failure modes common in mechanical relay and photo relay components.
The primary side of the device is powered by only 5mA of input current and incorporates a fail-safe EN pin preventing any possibility of back powering the VDD supply. In most applications, the VDD pin of the device should be connected to a system supply between 4.5V to 20V and the EN pin of the device should be driven by a GPIO output with Logic high between 2.1V to 20V. In other applications, the VDD and EN pins could be driven together driven together directly from the system supply or from a GPIO output.
The secondary side consists of back-to-back MOSFETs with a standoff voltage of ±600V from S1 to S2. The TPSI2260-Q1 MOSFET avalanche robustness and thermally conscious package design allow it to robustly support system level dielectric withstand testing (HiPot) and DC fast charger surge currents of up to 1mA (3mA for TPSI2260T-Q1)without requiring any external components.
The TPSI2260-Q1 is an isolated solid state relay designed for high voltage automotive and industrial applications. The TPSI2260-Q1 uses TIs high reliability reinforced capacitive isolation technology in combination with internal back-to-back MOSFETs to form a completely integrated solution requiring no secondary side power supply. The TPSI2260-Q1 improves system reliability as TIs capacitive isolation technology does not suffer from mechanical wearout or photo degradation failure modes common in mechanical relay and photo relay components.
The primary side of the device is powered by only 5mA of input current and incorporates a fail-safe EN pin preventing any possibility of back powering the VDD supply. In most applications, the VDD pin of the device should be connected to a system supply between 4.5V to 20V and the EN pin of the device should be driven by a GPIO output with Logic high between 2.1V to 20V. In other applications, the VDD and EN pins could be driven together driven together directly from the system supply or from a GPIO output.
The secondary side consists of back-to-back MOSFETs with a standoff voltage of ±600V from S1 to S2. The TPSI2260-Q1 MOSFET avalanche robustness and thermally conscious package design allow it to robustly support system level dielectric withstand testing (HiPot) and DC fast charger surge currents of up to 1mA (3mA for TPSI2260T-Q1)without requiring any external components.