DS90C363B
- No special start-up sequence required between clock/data and /PD pins. Input signal (clock and data) can be applied either before or after the device is powered.
- Support Spread Spectrum Clocking up to 100kHz frequency modulation and deviations of ±2.5% center spread or −5% down spread.
- "Input Clock Detection" feature will pull all LVDS pairs to logic low when input clock is missing and when /PD pin is logic high.
- 18 to 68 MHz shift clock support
- Best–in–Class Set & Hold Times on TxINPUTs
- Tx power consumption < 130 mW (typ) at 65MHz Grayscale
- 40% Less Power Dissipation than BiCMOS Alternatives
- Tx Power-down mode < 37μW (typ)
- Supports VGA, SVGA, XGA and Dual Pixel SXGA.
- Narrow bus reduces cable size and cost
- Up to 1.3 Gbps throughput
- Up to 170 Megabytes/sec bandwidth
- 345 mV (typ) swing LVDS devices for low EMI
- PLL requires no external components
- Compatible with TIA/EIA-644 LVDS standard
- Low profile 48-lead TSSOP package
- Improved replacement for:
- SN75LVDS84, DS90C363A
All trademarks are the property of their respective owners. TRI-STATE is a trademark of Texas Instruments. TRI-STATE is a trademark of Texas Instruments.
The DS90C363B transmitter converts 21 bits of CMOS/TTL data into three LVDS (Low Voltage Differential Signaling) data streams. A phase-locked transmit clock is transmitted in parallel with the data streams over a fourth LVDS link. Every cycle of the transmit clock 21 bits of input data are sampled and transmitted. At a transmit clock frequency of 65 MHz, 18 bits of RGB data and 3 bits of LCD timing and control data (FPLINE, FPFRAME, DRDY) are transmitted at a rate of 455 Mbps per LVDS data channel. Using a 65 MHz clock, the data throughput is 170 Mbytes/sec. The DS90C363B transmitter can be programmed for Rising edge strobe or Falling edge strobe through a dedicated pin. A Rising edge or Falling edge strobe transmitter will interoperate with a Falling edge strobe Receiver (DS90CF366) without any translation logic.
This chipset is an ideal means to solve EMI and cable size problems associated with wide, high speed TTL interfaces.
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | DS90C363B 3.3V Prog LVDS Transm 18-Bit FPD Link -65 MHz 数据表 (Rev. F) | 2013-4-12 | |||
| 应用手册 | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018-11-9 | ||||
| 应用手册 | How to Map RGB Signals to LVDS/OpenLDI(OLDI) Displays (Rev. A) | 2018-6-29 | ||||
| 应用手册 | AN-1032 An Introduction to FPD-Link (Rev. C) | 2017-8-8 | ||||
| 应用手册 | Receiver Skew Margin for Channel Link I and FPD Link I Devices | PDF | HTML | 2016-1-13 | |||
| 应用手册 | TFT Data Mapping for Dual Pixel LDI Application - Alternate A - Color Map | 2004-5-15 | ||||
| 应用手册 | AN-1056 STN Application Using FPD-Link | 2004-5-14 | ||||
| 应用手册 | AN-1085 FPD-Link PCB and Interconnect Design-In Guidelines | 2004-5-14 |
设计与开发
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FLINK3V8BT-85 — 用于 FPD 链接系列串行器和解串器 LVDS 器件的评估套件
FPD-Link evaluation kit contains a Transmitter (Tx) board, a Receiver (Rx) board along with interfacing cables. This kit will demonstrate the chipsets interfacing from test equipment or a graphics controller using Low Voltage Differential Signaling (LVDS) to a receiver board.
The Transmitter board (...)
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| TSSOP (DGG) | 48 | Ultra Librarian |
订购和质量
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