DS90CR286A
- 20 to 66 MHz Shift Clock Support
- 50% Duty Cycle on Receiver Output Clock
- Best–in–Class Set and Hold Times on Rx Outputs
- Rx Power Consumption < 270 mW (Typ) at 66
MHz Worst Case - Rx Power-Down Mode < 200 µW (Max)
- ESD Rating > 7 kV (HBM), > 700 V (EIAJ)
- PLL Requires No External Components
- Compatible with TIA/EIA-644 LVDS Standard
- Low Profile 56-Pin or 48-Pin DGG (TSSOP)
Package - Operating Temperature: −40°C to 85°C
- Automotive Q Grade Available – AEC-Q100 Grade
3 Qualified
The DS90CR286A receiver converts the four LVDS data streams back into parallel 28 bits of LVCMOS data. Also available is the DS90CR216A receiver that converts the three LVDS data streams back into parallel 21 bits of LVCMOS data. The outputs of both receivers strobe on the rising edge.
The receiver LVDS clock operates at rates from 20 to 66 MHz. The device phase-locks to the input clock, samples the serial bit streams at the LVDS data lines, and converts them into parallel output data. At an incoming clock rate of 66 MHz, each LVDS input line is running at a bit rate of 462 Mbps, resulting in a maximum throughput of 1.848 Gbps for the DS90CR286A and 1.386 Gbps for the DS90CR216A.
The DS90CR286A and DS90CR216A devices are enhanced over prior generation receivers and provide a wider data valid time on the receiver output. The use of these serial link devices is ideal for solving EMI and cable size problems associated with transmitting data over wide, high speed parallel LVCMOS interfaces. Both devices are offered in TSSOP packages.
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技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | DS90CR286A/-Q1 (or DS90CR216A) 3.3-V Rising Edge Data Strobe LVDS Receiver 28-Bit (or 21-Bit) Channel Link-66 MHz 数据表 (Rev. H) | PDF | HTML | 2016-1-18 | ||
| 应用手册 | High-Speed Layout Guidelines for Reducing EMI for LVDS SerDes Designs | 2018-11-9 | ||||
| 应用手册 | AN-1108 Channel-Link PCB and Interconnect Design-In Guidelines (Rev. A) | 2018-8-3 | ||||
| 应用手册 | Receiver Skew Margin for Channel Link I and FPD Link I Devices | PDF | HTML | 2016-1-13 | |||
| 设计指南 | Channel Link I Design Guide | 2007-3-29 | ||||
| 应用手册 | Multi-Drop Channel-Link Operation | 2004-10-4 | ||||
| 应用手册 | CHANNEL LINK Moving and Shaping Information In Point-To-Point Applications | 1998-10-5 |
设计与开发
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FLINK3V8BT-85 — 用于 FPD 链接系列串行器和解串器 LVDS 器件的评估套件
FPD-Link evaluation kit contains a Transmitter (Tx) board, a Receiver (Rx) board along with interfacing cables. This kit will demonstrate the chipsets interfacing from test equipment or a graphics controller using Low Voltage Differential Signaling (LVDS) to a receiver board.
The Transmitter board (...)
| 封装 | 引脚 | CAD 符号、封装和 3D 模型 |
|---|---|---|
| TSSOP (DGG) | 56 | Ultra Librarian |