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UCC27532-Q1

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Automotive 2.5-A/5-A single-channel gate driver with 8-V UVLO, 35-V VDD, and CMOS inputs

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Data sheet

UCC27532-Q1

ACTIVE
Data sheet Order now

Product details

Number of channels 1 Power switch IGBT, MOSFET Peak output current (A) 5 Input supply voltage (min) (V) 10 Input supply voltage (max) (V) 32 Features Split Output Operating temperature range (°C) -40 to 140 Rise time (ns) 15 Fall time (ns) 7 Propagation delay time (µs) 0.017 Input threshold CMOS Channel input logic Non-Inverting, Single Input negative voltage (V) -5 Rating Automotive Undervoltage lockout (typ) (V) 8 Driver configuration Single input
Number of channels 1 Power switch IGBT, MOSFET Peak output current (A) 5 Input supply voltage (min) (V) 10 Input supply voltage (max) (V) 32 Features Split Output Operating temperature range (°C) -40 to 140 Rise time (ns) 15 Fall time (ns) 7 Propagation delay time (µs) 0.017 Input threshold CMOS Channel input logic Non-Inverting, Single Input negative voltage (V) -5 Rating Automotive Undervoltage lockout (typ) (V) 8 Driver configuration Single input
SOT-23 (DBV) 6 8.12 mm² 2.9 x 2.8
  • Qualified for automotive applications
  • AEC-Q100 qualified with the following results:
    • Device temperature grade 1
  • Low-cost gate driver (offering optimal solution for driving FET and IGBTs)
  • Superior replacement to discrete transistor pair drive (providing easy interface with controller)
  • CMOS compatible input-logic threshold (becomes fixed at VDD above 18V)
  • Split outputs allow separate turnon and turnoff tuning
  • Enable with Fixed TTL compatible threshold
  • High 2.5A source and 5A sink peak-drive currents at 18V VDD
  • Wide VDD range from 10V up to 35V
  • Input pins capable of withstanding up to –5V DC below ground
  • Output held low when inputs are floating or during VDD UVLO
  • Fast propagation delays (17ns typical)
  • Fast rise and fall times (15ns and 7ns typical with 1800pF load)
  • Undervoltage lockout (UVLO)
  • Used as a high-side or low-side driver (if designed with proper bias and signal isolation)
  • Low-cost space-saving 6-pin DBV (SOT-23) package
  • Operating temperature range of –40°C to 140°C
  • Qualified for automotive applications
  • AEC-Q100 qualified with the following results:
    • Device temperature grade 1
  • Low-cost gate driver (offering optimal solution for driving FET and IGBTs)
  • Superior replacement to discrete transistor pair drive (providing easy interface with controller)
  • CMOS compatible input-logic threshold (becomes fixed at VDD above 18V)
  • Split outputs allow separate turnon and turnoff tuning
  • Enable with Fixed TTL compatible threshold
  • High 2.5A source and 5A sink peak-drive currents at 18V VDD
  • Wide VDD range from 10V up to 35V
  • Input pins capable of withstanding up to –5V DC below ground
  • Output held low when inputs are floating or during VDD UVLO
  • Fast propagation delays (17ns typical)
  • Fast rise and fall times (15ns and 7ns typical with 1800pF load)
  • Undervoltage lockout (UVLO)
  • Used as a high-side or low-side driver (if designed with proper bias and signal isolation)
  • Low-cost space-saving 6-pin DBV (SOT-23) package
  • Operating temperature range of –40°C to 140°C

The UCC27532-Q1 device is a single-channel high-speed gate driver capable of effectively driving MOSFET and IGBT power switches by up to 2.5A source and 5A sink (asymmetrical drive) peak current. Strong sink capability in asymmetrical drive boosts immunity against parasitic Miller turnon effect. The UCC27532-Q1 device also features a split-output configuration where the gate-drive current is sourced through the OUTH pin and sunk through the OUTL pin. This pin arrangement allows the user to apply independent turnon and turnoff resistors to the OUTH and OUTL pins respectively and easily control the switching slew rates.

The driver has rail-to-rail drive capability and an extremely-small propagation delay of 17ns (typically).

The UCC27532-Q1 device has a CMOS-input threshold-centered 55% rise and 45% fall in regards of VDD at VDD below or equal 18V. When VDD is above 18V, the input threshold remains fixed at the maximum level.

The driver has an EN pin with a fixed TTL-compatible threshold. EN is internally pulled up; pulling EN low disables driver, while leaving it open provides normal operation. The EN pin can be used as an additional input with the same performance as the IN pin.

Leaving the input pin of driver open holds the output low. The logic behavior of the driver is shown in the Timing Diagram, Input/Output Logic Truth Table, and .

Internal circuitry on the VDD pin provides an undervoltage-lockout function that holds the output low until the VDD supply voltage is within operating range.

The UCC27532-Q1 driver is offered in a 6-pin standard SOT-23 (DBV) package. The device operates over a wide temperature range of –40°C to 140°C.

The UCC27532-Q1 device is a single-channel high-speed gate driver capable of effectively driving MOSFET and IGBT power switches by up to 2.5A source and 5A sink (asymmetrical drive) peak current. Strong sink capability in asymmetrical drive boosts immunity against parasitic Miller turnon effect. The UCC27532-Q1 device also features a split-output configuration where the gate-drive current is sourced through the OUTH pin and sunk through the OUTL pin. This pin arrangement allows the user to apply independent turnon and turnoff resistors to the OUTH and OUTL pins respectively and easily control the switching slew rates.

The driver has rail-to-rail drive capability and an extremely-small propagation delay of 17ns (typically).

The UCC27532-Q1 device has a CMOS-input threshold-centered 55% rise and 45% fall in regards of VDD at VDD below or equal 18V. When VDD is above 18V, the input threshold remains fixed at the maximum level.

The driver has an EN pin with a fixed TTL-compatible threshold. EN is internally pulled up; pulling EN low disables driver, while leaving it open provides normal operation. The EN pin can be used as an additional input with the same performance as the IN pin.

Leaving the input pin of driver open holds the output low. The logic behavior of the driver is shown in the Timing Diagram, Input/Output Logic Truth Table, and .

Internal circuitry on the VDD pin provides an undervoltage-lockout function that holds the output low until the VDD supply voltage is within operating range.

The UCC27532-Q1 driver is offered in a 6-pin standard SOT-23 (DBV) package. The device operates over a wide temperature range of –40°C to 140°C.
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Type Title Date
* Data sheet UCC27532-Q1 2.5A and 5A, 35VMAX VDD Fet and IGBT Single-Gate Driver datasheet (Rev. C) PDF | HTML 27 Sep 2024
Application brief External Gate Resistor Selection Guide (Rev. A) 28 Feb 2020
Application brief Understanding Peak IOH and IOL Currents (Rev. A) 28 Feb 2020
Application brief High-Side Cutoff Switches for High-Power Automotive Applications (Rev. A) 26 Nov 2018
More literature Fundamentals of MOSFET and IGBT Gate Driver Circuits (Replaces SLUP169) (Rev. A) 29 Oct 2018

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Low-side drivers
UCC27531 — 2.5-A/5-A single-channel gate driver with 8-V UVLO, 35-V VDD, and split outputs UCC27531-Q1 — Automotive 2.5-A/5-A single-channel gate driver with 8-V UVLO, 35-V VDD, and split outputs UCC27532 — 2.5-A/5-A single-channel gate driver with 8-V UVLO, 35-V VDD, CMOS inputs, and split outputs UCC27532-Q1 — Automotive 2.5-A/5-A single-channel gate driver with 8-V UVLO, 35-V VDD, and CMOS inputs UCC27533 — 2.5-A/5-A single-channel gate driver with 8-V UVLO, 35-V VDD, and inverting/non-inverting inputs UCC27536 — 2.5-A/5-A single-channel gate driver with 8-V UVLO, 35-V VDD, and inverting input UCC27537 — 2.5-A/5-A single-channel gate driver with 8-V UVLO, 35-V VDD, and EN pin UCC27538 — 2.5-A/5-A single-channel gate driver with 8-V UVLO, 35-V VDD, and dual input
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