SMJ320C6203
- High-Performance Fixed-Point Digital Signal
Processor (DSP) SMJ320C62x™- 5-ns Instruction Cycle Time
- 200-MHz Clock Rate
- Eight 32-Bit Instructions/Cycle
- 1600 Million Instructions per Second (MIPS)
- 429-Pin Ball Grid Array (BGA) Package (GLP
Suffix) - VelociTI™ Advanced Very-Long-Instruction-Word
(VLIW) C62x DSP Core- Eight Highly-Independent Functional Units:
- Six Arithmetic Logic Units (ALUs) (32-/40-
Bit) - Two 16-Bit Multipliers (32-Bit Result)
- Six Arithmetic Logic Units (ALUs) (32-/40-
- Load-Store Architecture With 32 32-Bit
General-Purpose Registers - Instruction Packing Reduces Code Size
- All Instructions Conditional
- Eight Highly-Independent Functional Units:
- Instruction Set Features
- Byte-Addressable (8-, 16-, 32-Bit Data)
- 8-Bit Overflow Protection
- Saturation
- Bit-Field Extract, Set, Clear
- Bit-Counting
- Normalization
- 7Mb On-Chip SRAM
- 3Mb Internal Program/Cache (96K 32-Bit
Instructions) - 4Mb Dual-Access Internal Data (512KB)
- Organized as Two 256KB Blocks for Improved
Concurrency
- 3Mb Internal Program/Cache (96K 32-Bit
- Flexible Phase-Locked-Loop (PLL) Clock
Generator - 32-Bit External Memory Interface (EMIF)
- Glueless Interface to Synchronous Memories:
SDRAM or SBSRAM - Glueless Interface to Asynchronous Memories:
SRAM and EPROM - 52MB Addressable External Memory Space
- Glueless Interface to Synchronous Memories:
- Four-Channel Bootloading Direct-Memory-Access
(DMA) Controller With an Auxiliary Channel - 32-Bit Expansion Bus − Glueless/Low-Glue
- Glueless/Low-Glue Interface to Popular
Synchronous or Asynchronous Microprocessor
Buses- Master/Slave Functionality
- Glueless Interface to Synchronous FIFOs and
Asynchronous Peripherals- Three Multichannel Buffered Serial Ports
(McBSPs)- Direct Interface to T1/E1, MVIP, SCSA
Framers - ST-Bus-Switching Compatible
- Up to 256 Channels Each
- AC97-Compatible
- Serial-Peripheral Interface (SPI) Compatible
(Motorola®)
- Two 32-Bit General-Purpose Timers
- IEEE-1149.1 (JTAG(2)) Boundary-Scan-
Compatible- 0.15-µm/5-Level Metal Process
- CMOS Technology
- 3.3-V I/Os, 1.5-V Internal
- Glueless/Low-Glue Interface to Popular
All trademarks are the property of their respective owners.
The SMJ320C6203 device is part of the SMJ320C62x fixed-point DSP generation in the SMJ320C6000 DSP platform. The C62x DSP devices are based on the high-performance, advanced VelociTI VLIW architecture developed by TI, making these DSPs an excellent choice for multichannel and multifunction applications.
The SMJ320C62x DSP offers cost-effective solutions to high-performance DSP-programming challenges. The SMJ320C6203 has a performance capability of up to 1600 MIPS at a clock rate of 200 MHz. The C6203 DSP possesses the operational flexibility of high-speed controllers and the numerical capability of array processors. This processor has 32 general-purpose registers of 32-bit word length and eight highly-independent functional units.
The eight functional units provide six ALUs for a high degree of parallelism and two 16-bit multipliers for a 32-bit result. The C6203 can produce two multiply-accumulates (MACs) per cycle for a total of 400 million MACs per second (MMACS). The C6203 DSP also has application-specific hardware logic, on-chip memory, and additional on-chip peripherals. The C6203 device program memory consists of two blocks, with a 256KB block configured as memory-mapped program space, and the other 128KB block user-configurable as cache or memory-mapped program space. Data memory for the C6203 consists of two 256KB blocks of RAM.
The C6203 device has a powerful and diverse set of peripherals. The peripheral set includes three McBSPs, two general-purpose timers, a 32-bit expansion bus that offers ease of interface to synchronous or asynchronous industry-standard host bus protocols, and a glueless 32-bit EMIF capable of interfacing to SDRAM or SBSRAM and asynchronous peripherals.
The C62x devices have a complete set of development tools that includes: a new C compiler, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.
TI 不提供设计支持
TI 不会为该产品的新工程（例如新内容或软件更新）提供持续的设计支持。如可用，您将在此页面找到相关的配套资料、工具和软件。
技术文档
| 顶层文档 | 类型 | 标题 | 格式选项 | 下载最新的英语版本 | 日期 | |
|---|---|---|---|---|---|---|
| * | 数据表 | SMJ320C6203 Fixed-Point Digital Signal Processor 数据表 (Rev. A) | PDF | HTML | 2016-5-24 | ||
| * | 勘误表 | TMS320C6203, TMS320C6203B DSPs Silicon Errata (Silicon Rev. 1.x, 2.x, 3.0, 3.1) (Rev. L) | 2004-2-16 | |||
| * | SMD | SMJ320C6203 SMD 5962-00510 | 2016-6-21 | |||
| 应用手册 | Introduction to TMS320C6000 DSP Optimization | 2011-10-6 | ||||
| 更多文献资料 | SMJ320C6203GLPM20/5962-0051001QXA (Rev. A) | 2002-5-3 | ||||
| 更多文献资料 | Military C6000 DSPs (Rev. A) | 2000-5-8 |
设计与开发
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