This guide has three main parts. The first part is the preparation work before debugging. Sometimes the preparation work can take an hour or more, but good preparation decreases overall debugging time. The second part of the guide covers the first part of the debug process: narrowing down what is causing the issue. PoE plus DC/DC designs can be broken up into sections, and this application report guides you through how to check if one or more of these sections are suspect in the problem. The third part of this guide covers common issues and common resolutions. For example, if the design has the parallel MOSFET in an active clamp forward that breaks during shutdown, what are the issues that usually cause that? This list is not exhaustive because there are many components in PoE designs and they can break in different ways and for different reasons. However, this guide should aid in the first steps of the debug process for most PoE designs.

Part of the current TI strategy is to provide working reference designs that can be copied. The first recommendation is to find the closest reference design possible to the design being worked on. Look for the same IC, the same topology (for example, synchronous flyback), and the same output voltage and power level. If there is not a close design, contact the PoE applications engineer through E2E for an internal search. Next, evaluate any parts that are different, whether it be a transformer, a MOSFET, a resistor size, and so forth. Question why the part is different. List all the reasons how these parts are different (for example, different gate capacitance, different reverse recovery time, different voltage rating, different package size). These may be the first clues to why the design is experiencing problems, but the TI reference design is not. Review the PoE PD Schematic Review Guidelines application report for component variations.