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CDCLVD1216

ACTIVE

Low jitter, 2-input selectable 1:16 universal-to-LVDS buffer

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Data sheet

CDCLVD1216

ACTIVE
Data sheet Order now

Product details

Function Differential Additive RMS jitter (typ) (fs) 171 Output frequency (max) (MHz) 800 Number of outputs 16 Output supply voltage (V) 2.5 Core supply voltage (V) 2.5 Output skew (ps) 55 Features 2:16 fanout, Universal inputs Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL
Function Differential Additive RMS jitter (typ) (fs) 171 Output frequency (max) (MHz) 800 Number of outputs 16 Output supply voltage (V) 2.5 Core supply voltage (V) 2.5 Output skew (ps) 55 Features 2:16 fanout, Universal inputs Operating temperature range (°C) -40 to 85 Rating Catalog Output type LVDS Input type LVCMOS, LVDS, LVPECL
VQFN (RGZ) 48 49 mm² 7 x 7
  • 2:16 Differential Buffer
  • Low Additive Jitter: <300 fs RMS in
    10 kHz to 20 MHz
  • Low Output Skew of 55 ps (Max)
  • Universal Inputs Accept LVDS, LVPECL, LVCMOS
  • Selectable Clock Inputs Through Control Pin
  • 16 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
  • Clock Frequency up to 800 MHz
  • 2.375–2.625V Device Power Supply
  • LVDS Reference Voltage, VAC_REF,
    Available for Capacitive Coupled Inputs
  • Industrial Temperature Range –40°C to 85°C
  • Packaged in 7mm × 7mm 48-Pin QFN (RGZ)
  • ESD Protection Exceeds 3 kV HBM, 1 kV CDM
  • APPLICATIONS
    • Telecommunications/Networking
    • Medical Imaging
    • Test and Measurement Equipment
    • Wireless Communications
    • General Purpose Clocking
  • 2:16 Differential Buffer
  • Low Additive Jitter: <300 fs RMS in
    10 kHz to 20 MHz
  • Low Output Skew of 55 ps (Max)
  • Universal Inputs Accept LVDS, LVPECL, LVCMOS
  • Selectable Clock Inputs Through Control Pin
  • 16 LVDS Outputs, ANSI EIA/TIA-644A Standard Compatible
  • Clock Frequency up to 800 MHz
  • 2.375–2.625V Device Power Supply
  • LVDS Reference Voltage, VAC_REF,
    Available for Capacitive Coupled Inputs
  • Industrial Temperature Range –40°C to 85°C
  • Packaged in 7mm × 7mm 48-Pin QFN (RGZ)
  • ESD Protection Exceeds 3 kV HBM, 1 kV CDM
  • APPLICATIONS
    • Telecommunications/Networking
    • Medical Imaging
    • Test and Measurement Equipment
    • Wireless Communications
    • General Purpose Clocking

The CDCLVD1216 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 16 pairs of differential LVDS clock outputs (OUT0, OUT15) with minimum skew for clock distribution. The CDCLVD1216 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1216 is specifically designed for driving 50 Ω transmission lines. If driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open it disables the outputs (static). The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5 V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1216 is packaged in small 48-pin, 7mm × 7mm QFN package.

The CDCLVD1216 clock buffer distributes one of two selectable clock inputs (IN0, IN1) to 16 pairs of differential LVDS clock outputs (OUT0, OUT15) with minimum skew for clock distribution. The CDCLVD1216 can accept two clock sources into an input multiplexer. The inputs can either be LVDS, LVPECL, or LVCMOS.

The CDCLVD1216 is specifically designed for driving 50 Ω transmission lines. If driving the inputs in single ended mode, the appropriate bias voltage (VAC_REF) should be applied to the unused negative input pin.

The IN_SEL pin selects the input which is routed to the outputs. If this pin is left open it disables the outputs (static). The part supports a fail safe function. It incorporates an input hysteresis, which prevents random oscillation of the outputs in absence of an input signal.

The device operates in 2.5 V supply environment and is characterized from –40°C to 85°C (ambient temperature). The CDCLVD1216 is packaged in small 48-pin, 7mm × 7mm QFN package.
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Type Title Date
* Data sheet 2:16 Low Additive Jitter LVDS Buffer datasheet (Rev. B) 17 Jan 2011

Design & development

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Simulation model

CDCLVD1216 IBIS Model (Rev. C)

SLLM092C.ZIP (15 KB) - IBIS Model
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