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LMK00334

ACTIVE

4-output PCIe® Gen 1 to Gen 7 clock buffer and level translator

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Data sheet

LMK00334

ACTIVE
Data sheet Order now

Product details

Number of outputs 4 Additive RMS jitter (typ) (fs) 30 Core supply voltage (V) 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 50 Operating temperature range (°C) -40 to 85 Rating Catalog Output type HCSL, LVCMOS Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL, XTAL
Number of outputs 4 Additive RMS jitter (typ) (fs) 30 Core supply voltage (V) 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 50 Operating temperature range (°C) -40 to 85 Rating Catalog Output type HCSL, LVCMOS Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, SSTL, XTAL
WQFN (RTV) 32 25 mm² 5 x 5
  • 3:1 Input multiplexer
    • Two universal inputs operate up to 400MHz and accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or single-ended clocks
    • One crystal input accepts a 10MHz to 40MHz crystal or single-ended clock
  • Two banks with two differential outputs each
    • HCSL, or Hi-Z (selectable)
    • Additive RMS phase jitter for PCIe Specification
      • 7.2fs RMS for Gen 5 (typical)
      • 5fs RMS for Gen 6 (typical)
      • 3.5fs RMS for Gen 7 (typical)
  • High PSRR: –72dBc at 156.25MHz
  • LVCMOS output with synchronous enable input
  • Pin-controlled configuration
  • VCC core supply: 3.3V ± 5%
  • Three independent VCCO output supplies: 3.3V, 2.5V ± 5%
  • Industrial temperature range: –40°C to +105°C
  • 32-pin WQFN (5mm × 5mm)
  • 3:1 Input multiplexer
    • Two universal inputs operate up to 400MHz and accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or single-ended clocks
    • One crystal input accepts a 10MHz to 40MHz crystal or single-ended clock
  • Two banks with two differential outputs each
    • HCSL, or Hi-Z (selectable)
    • Additive RMS phase jitter for PCIe Specification
      • 7.2fs RMS for Gen 5 (typical)
      • 5fs RMS for Gen 6 (typical)
      • 3.5fs RMS for Gen 7 (typical)
  • High PSRR: –72dBc at 156.25MHz
  • LVCMOS output with synchronous enable input
  • Pin-controlled configuration
  • VCC core supply: 3.3V ± 5%
  • Three independent VCCO output supplies: 3.3V, 2.5V ± 5%
  • Industrial temperature range: –40°C to +105°C
  • 32-pin WQFN (5mm × 5mm)

The LMK00334 device is a 4-output HCSL fanout buffer intended for high-frequency, low-jitter clock, data distribution, and level translation. The device is capable of distributing the reference clock for ADCs, DACs, multi-gigabit Ethernet, XAUI, fibre channel, SATA/SAS, SONET/SDH, CPRI, and high-frequency backplanes.

The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of two HCSL outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00334 operates from a 3.3V core supply and three independent 3.3V or 2.5V output supplies.

The LMK00334 provides high performance, versatility, and power efficiency, making the device designed for replacing fixed-output buffer devices while increasing timing margin in the system.

The LMK00334 device is a 4-output HCSL fanout buffer intended for high-frequency, low-jitter clock, data distribution, and level translation. The device is capable of distributing the reference clock for ADCs, DACs, multi-gigabit Ethernet, XAUI, fibre channel, SATA/SAS, SONET/SDH, CPRI, and high-frequency backplanes.

The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of two HCSL outputs and one LVCMOS output. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00334 operates from a 3.3V core supply and three independent 3.3V or 2.5V output supplies.

The LMK00334 provides high performance, versatility, and power efficiency, making the device designed for replacing fixed-output buffer devices while increasing timing margin in the system.
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* Data sheet LMK00334 Four-Output Clock Buffer and Level Translator for PCIe® Gen 1 to Gen 7 datasheet (Rev. F) PDF | HTML 05 Aug 2025
Application note LMK0033x PCI Express Compliance Report PDF | HTML 05 May 2025
Application note Clocking for PCIe Applications PDF | HTML 28 Nov 2023

Design & development

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Evaluation board

LMK00338EVM — LMK00338 PCIe Gen1/2/3 Clock Buffer Evaluation Module

The LMK00338 is a 400MHz, 8-output HCSL buffer intended for PCIe Gen1/2/3 Applications, low additive jitter clock distribution and level translation. The EVM allows the user to verify the functionality and performance specification of the device. Refer to the LMK00338 datasheet for the functional (...)

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LMK00334 IBIS Model

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