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LMK00306

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3.1-GHz differential clock buffer/level translator with 6 configurable outputs

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Data sheet

LMK00306

ACTIVE
Data sheet Order now

Product details

Number of outputs 7 Additive RMS jitter (typ) (fs) 51 Core supply voltage (V) 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 50 Operating temperature range (°C) -40 to 85 Rating Catalog Output type HCSL, LVCMOS, LVDS, LVPECL Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, XTAL
Number of outputs 7 Additive RMS jitter (typ) (fs) 51 Core supply voltage (V) 3.3 Output supply voltage (V) 2.5, 3.3 Output skew (ps) 50 Operating temperature range (°C) -40 to 85 Rating Catalog Output type HCSL, LVCMOS, LVDS, LVPECL Input type CML, HCSL, HSTL, LVCMOS, LVDS, LVPECL, LVTTL, SSTL, XTAL
WQFN (NJK) 36 36 mm² 6 x 6
  • 3:1 Input Multiplexer
    • Two Universal Inputs Operate up to 3.1 GHz
      and Accept LVPECL, LVDS, CML, SSTL,
      HSTL, HCSL, or Single-Ended Clocks
    • One Crystal Input Accepts a 10 to 40 MHz
      Crystal or Single-Ended Clock
  • Two Banks with 3 Differential Outputs Each
    • LVPECL, LVDS, HCSL, or Hi-Z (Selectable
      Per Bank)
    • LVPECL Additive Jitter with LMK03806 Clock
      Source at 156.25 MHz:
      • 20 fs RMS (10 kHz to 1 MHz)
      • 51 fs RMS (12 kHz to 20 MHz)
  • High PSRR: –65 / –76 dBc (LVPECL/LVDS) at
    156.25 MHz
  • LVCMOS Output with Synchronous Enable Input
  • Pin-Controlled Configuration
  • VCC Core Supply: 3.3 V ± 5%
  • 3 Independent VCCO Output Supplies: 3.3 V/2.5 V
    ± 5%
  • Industrial Temperature Range: –40°C to +85°C
  • 36-lead WQFN (6 mm × 6 mm)
  • 3:1 Input Multiplexer
    • Two Universal Inputs Operate up to 3.1 GHz
      and Accept LVPECL, LVDS, CML, SSTL,
      HSTL, HCSL, or Single-Ended Clocks
    • One Crystal Input Accepts a 10 to 40 MHz
      Crystal or Single-Ended Clock
  • Two Banks with 3 Differential Outputs Each
    • LVPECL, LVDS, HCSL, or Hi-Z (Selectable
      Per Bank)
    • LVPECL Additive Jitter with LMK03806 Clock
      Source at 156.25 MHz:
      • 20 fs RMS (10 kHz to 1 MHz)
      • 51 fs RMS (12 kHz to 20 MHz)
  • High PSRR: –65 / –76 dBc (LVPECL/LVDS) at
    156.25 MHz
  • LVCMOS Output with Synchronous Enable Input
  • Pin-Controlled Configuration
  • VCC Core Supply: 3.3 V ± 5%
  • 3 Independent VCCO Output Supplies: 3.3 V/2.5 V
    ± 5%
  • Industrial Temperature Range: –40°C to +85°C
  • 36-lead WQFN (6 mm × 6 mm)

The LMK00306 is a 3-GHz, 6-output differential fanout buffer intended for high-frequency, low-jitter clock/data distribution and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 3 differential outputs and one LVCMOS output. Both differential output banks can be independently configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00306 operates from a 3.3 V core supply and 3 independent 3.3 V/2.5 V output supplies.

The LMK00306 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.

The LMK00306 is a 3-GHz, 6-output differential fanout buffer intended for high-frequency, low-jitter clock/data distribution and level translation. The input clock can be selected from two universal inputs or one crystal input. The selected input clock is distributed to two banks of 3 differential outputs and one LVCMOS output. Both differential output banks can be independently configured as LVPECL, LVDS, or HCSL drivers, or disabled. The LVCMOS output has a synchronous enable input for runt-pulse-free operation when enabled or disabled. The LMK00306 operates from a 3.3 V core supply and 3 independent 3.3 V/2.5 V output supplies.

The LMK00306 provides high performance, versatility, and power efficiency, making it ideal for replacing fixed-output buffer devices while increasing timing margin in the system.
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* Data sheet LMK00306 3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator datasheet (Rev. D) PDF | HTML 28 Mar 2016
Application note Sine to Square Wave Conversion Using Clock Buffers PDF | HTML 03 Sep 2024
Application note Clocking for PCIe Applications PDF | HTML 28 Nov 2023

Design & development

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Evaluation board

LMK00306EVM — LMK00306 evaluation board

The LMK00306 Evaluation Board allows functional and performance verification of the LMK00306 high-performance 6-output differential clock buffer device.

User guide: PDF
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Support software

CLOCKDESIGNTOOL — Clock Design Tool Software

The Clock Design Tool software helps with part selection, loop filter design and simulation of timing device solutions. When you enter desired output frequencies and a reference frequency (optional), the tool provides TI devices to meet the specified requirements, divider values and a recommended (...)

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Simulation model

LMK00306 IBIS Model (Rev. A)

SNAM049A.ZIP (105 KB) - IBIS Model
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Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

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PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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WQFN (NJK) 36 Ultra Librarian
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