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LMK05318B-Q1

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Automotive ultra-low jitter network synchronizer and clock generator

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Data sheet

LMK05318B-Q1

ACTIVE
Data sheet Order now

Product details

Function Clock network synchronizer Number of outputs 8 Output type CML, HCSL, LVCMOS, LVDS, LVPECL RMS jitter (fs) 50 Features I2C, Integrated EEPROM, Pin programmable, SPI Output frequency (min) (MHz) 0.000001 Output frequency (max) (MHz) 800 Input type LVCMOS, LVDS, LVPECL, XTAL Supply voltage (min) (V) 3.135 Supply voltage (max) (V) 3.465 Operating temperature range (°C) -40 to 125 Number of input channels 2
Function Clock network synchronizer Number of outputs 8 Output type CML, HCSL, LVCMOS, LVDS, LVPECL RMS jitter (fs) 50 Features I2C, Integrated EEPROM, Pin programmable, SPI Output frequency (min) (MHz) 0.000001 Output frequency (max) (MHz) 800 Input type LVCMOS, LVDS, LVPECL, XTAL Supply voltage (min) (V) 3.135 Supply voltage (max) (V) 3.465 Operating temperature range (°C) -40 to 125 Number of input channels 2
VQFN (RGZ) 48 49 mm² 7 x 7
  • AEC-Q100 qualified for automotive applications
    • –40°C to 105°C operating temperature (Grade 2)
  • Ultra-low jitter BAW VCO based Ethernet clocks
    • 32fs typical RMS jitter at 312.5MHz with 4MHz 1st order high-pass filter (HPF)
    • 44fs typical RMS jitter at 156.25MHz with 4MHz 1st order HPF
    • 50fs typical/ 80fs maximum RMS jitter at 312.5MHz
    • 60fs typical/ 90fs maximum RMS jitter at 156.25MHz
  • One high-performance Digital Phase-Locked Loop (DPLL) paired with two Analog Phase-Locked Loops (APLLs):
    • 1mHz to 4kHz programmable DPLL loop bandwidth
    • < 1ppt per step DCO adjustment for IEEE 1588 PTP clock steering
  • Two differential or single-ended DPLL inputs
    • 1Hz (1PPS) to 800MHz input frequency
    • Digital holdover and hitless switching
  • Eight differential outputs with programmable AC-LVPECL, AC-CML, AC-LVDS, HSCL, and 1.8V LVCMOS output formats.
    • 1Hz (1PPS) to 1250MHz output frequency
    • PCIe Gen 1 to 6 compliant
  • I2C, 3-wire SPI, or 4-wire SPI
  • 3.3V core supply and 1.8V, 2.5V, or 3.3V output supply
  • –40°C to +105°C operating temperature
  • AEC-Q100 qualified for automotive applications
    • –40°C to 105°C operating temperature (Grade 2)
  • Ultra-low jitter BAW VCO based Ethernet clocks
    • 32fs typical RMS jitter at 312.5MHz with 4MHz 1st order high-pass filter (HPF)
    • 44fs typical RMS jitter at 156.25MHz with 4MHz 1st order HPF
    • 50fs typical/ 80fs maximum RMS jitter at 312.5MHz
    • 60fs typical/ 90fs maximum RMS jitter at 156.25MHz
  • One high-performance Digital Phase-Locked Loop (DPLL) paired with two Analog Phase-Locked Loops (APLLs):
    • 1mHz to 4kHz programmable DPLL loop bandwidth
    • < 1ppt per step DCO adjustment for IEEE 1588 PTP clock steering
  • Two differential or single-ended DPLL inputs
    • 1Hz (1PPS) to 800MHz input frequency
    • Digital holdover and hitless switching
  • Eight differential outputs with programmable AC-LVPECL, AC-CML, AC-LVDS, HSCL, and 1.8V LVCMOS output formats.
    • 1Hz (1PPS) to 1250MHz output frequency
    • PCIe Gen 1 to 6 compliant
  • I2C, 3-wire SPI, or 4-wire SPI
  • 3.3V core supply and 1.8V, 2.5V, or 3.3V output supply
  • –40°C to +105°C operating temperature

The LMK05318B-Q1 is high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of Ethernet-based networking applications.

The device integrates one DPLL and two APLLs to provide hitless switching and jitter attenuation using the programmable loop bandwidths (LBWs) with one external loop filter capacitor to maximize the flexibility and ease of use.

APLL1 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology in VCO1 and can generate 312.5MHz output clocks with 50fs typical RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 features a conventional LC VCO to provide options for a second frequency and/or synchronization domain.

The integrated EEPROM can be used for custom system configurations on start-up. Internal LDO regulators provide excellent power supply noise rejection (PSNR) to reduce the cost and complexity of the power delivery network.

The LMK05318B-Q1 is high-performance network synchronizer and jitter cleaner designed to meet the stringent requirements of Ethernet-based networking applications.

The device integrates one DPLL and two APLLs to provide hitless switching and jitter attenuation using the programmable loop bandwidths (LBWs) with one external loop filter capacitor to maximize the flexibility and ease of use.

APLL1 features an ultra-high performance PLL with TI’s proprietary Bulk Acoustic Wave (BAW) technology in VCO1 and can generate 312.5MHz output clocks with 50fs typical RMS jitter (12kHz to 20MHz) irrespective of the DPLL reference input frequency and jitter characteristics. APLL2 features a conventional LC VCO to provide options for a second frequency and/or synchronization domain.

The integrated EEPROM can be used for custom system configurations on start-up. Internal LDO regulators provide excellent power supply noise rejection (PSNR) to reduce the cost and complexity of the power delivery network.
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* Data sheet LMK05318B-Q1 1-DPLL 2-APLL 2-IN 8-OUT Network Synchronizer With BAW VCO for Automotive and Industrial Applications datasheet (Rev. A) PDF | HTML 10 Dec 2025

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

LMK05318BEVM — Network synchronizer clock evaluation module

This is an evaluation module (EVM) for the LMK05318B network synchronizer clock device.
The EVM can be used as a flexible, synchronous clock source for rapid evaluation, compliance testing, and system prototyping. SMA ports provide access to the LMK05318B clock inputs and outputs for interfacing to (...)

User guide: PDF
Not available on TI.com
Design tool

CLOCK-TREE-ARCHITECT — Clock tree architect programming software

Clock tree architect is a clock tree synthesis tool that streamlines your design process by generating clock tree solutions based on your system requirements. The tool pulls data from an extensive database of clocking products to generate a system-level multi-chip clocking solution.
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Design tool

PLLATINUMSIM-SW — PLLatinum Sim Tool

PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.

Supported products & hardware

Supported products & hardware

Products
Clock buffers
  • CDCDB2000 — DB2000QL compliant 20-output clock buffer for PCIe® Gen 1 to Gen 7
  • CDCDB400 — 4-output clock buffer for PCIe® Gen 1 to Gen 7
  • CDCDB800 — 8-output clock buffer for PCIe® Gen 1 to Gen 7
  • CDCDB803 — 8-output clock buffer for PCIe® Gen 1 to Gen 6 with selectable SMBus addresses
  • CDCLVC1102 — Low jitter, 1:2 LVCMOS fan-out clock buffer
  • CDCLVC1103 — Low jitter, 1:3 LVCMOS fan-out clock buffer
  • CDCLVC1104 — Low jitter, 1:4 LVCMOS fan-out clock buffer
  • CDCLVC1106 — Low jitter, 1:6 LVCMOS fan-out clock buffer
  • CDCLVC1108 — Low jitter, 1:8 LVCMOS fan-out clock buffer
  • CDCLVC1110 — Low jitter, 1:10 LVCMOS fan-out clock buffer
  • CDCLVC1112 — Low jitter, 1:12 LVCMOS fan-out clock buffer
  • CDCLVC1310 — Universal input, 10-output low impedance LVCMOS buffer
  • CDCLVD110A — 1-to-10 LVDS clock buffer up to 1100-MHz with minimum skew for clock distribution
  • CDCLVD1204 — Low jitter, 2-input selectable 1:4 universal-to-LVDS buffer
  • CDCLVD1208 — Low jitter, 2-input selectable 1:8 universal-to-LVDS buffer
  • CDCLVD1212 — Low jitter, 2-input selectable 1:12 universal-to-LVDS buffer
  • CDCLVD1213 — Low jitter, 1:4 universal-to-LVDS buffer with selectable output divider
  • CDCLVD1216 — Low jitter, 2-input selectable 1:16 universal-to-LVDS buffer
  • CDCLVD2102 — Low jitter, dual 1:2 universal-to-LVDS buffer
  • CDCLVD2104 — Low jitter, dual 1:4 universal-to-LVDS buffer
  • CDCLVD2106 — Low jitter, dual 1:6 universal-to-LVDS buffer
  • CDCLVD2108 — Low jitter, dual 1:8 universal-to-LVDS buffer
  • CDCLVP110 — 1:10 LVPECL/HSTL to LVPECL clock driver
  • CDCLVP1102 — Low jitter 1:2 universal-to-LVPECL buffer
  • CDCLVP111 — 1:10 LVPECL buffer with selectable input
  • CDCLVP111-EP — HiRel, 1:10 LVPECL buffer with selectable input
  • CDCLVP111-SEP — Radiation-tolerant 1:10 LVPECL high-speed clock buffer with selectable input clock driver
  • CDCLVP111-SP — 1:10 high speed clock buffer with selectable input clock driver
  • CDCLVP1204 — Low-jitter, two-input, selectable 1:4 universal-to-LVPECL buffer
  • CDCLVP1208 — Low jitter, 2-input selectable 1:8 universal-to-LVPECL buffer
  • CDCLVP1212 — Low jitter, 2-input selectable 1:12 universal-to-LVPECL buffer
  • CDCLVP1216 — Low jitter, 2-input selectable 1:16 universal-to-LVPECL buffer
  • CDCLVP2102 — Low jitter, dual 1:2 universal-to-LVPECL buffer
  • CDCLVP2104 — Low jitter, dual 1:4 universal-to-LVPECL buffer
  • CDCLVP2106 — Low jitter, dual 1:6 universal-to-LVPECL buffer
  • CDCLVP2108 — Low jitter, dual 1:8 universal-to-LVPECL buffer
  • CDCLVP215 — Dual 1:5 high speed LVPECL fan out buffer
  • LMK00301 — 3-GHz, 10-output differential fanout buffer / level translator
  • LMK00304 — 3.1-GHz differential clock buffer/level translator with 4 configurable outputs
  • LMK00306 — 3.1-GHz differential clock buffer/level translator with 6 configurable outputs
  • LMK00308 — 3.1-GHz differential clock buffer/level translator with 8 configurable outputs
  • LMK00334 — 4-output PCIe® Gen 1 to Gen 7 clock buffer and level translator
  • LMK00334-Q1 — Automotive 4-output PCIe® Gen1/Gen2/Gen3/Gen4/Gen5 clock buffer and level translator
  • LMK00338 — 8-output PCIe® Gen 1 to Gen 7 clock buffer and level translator
  • LMK1C1102 — 2-channel output LVCMOS 1.8-V buffer
  • LMK1C1102A — 1.8V,2.5V or 3.3V asynchronous 2 channel output LVCMOS buffer
  • LMK1C1103 — 3-channel output LVCMOS 1.8-V buffer
  • LMK1C1103A — 1.8V,2.5V or 3.3V asynchronous 3 channel output LVCMOS buffer
  • LMK1C1104 — 4-channel output LVCMOS 1.8-V buffer
  • LMK1C1104A — 1.8V,2.5V or 3.3V asynchronous 4 channel output LVCMOS buffer
  • LMK1C1106 — 6-channel output LVCMOS 1.8-V buffer
  • LMK1C1106A — 1.8V,2.5V or 3.3V asynchronous 6 channel output LVCMOS buffer
  • LMK1C1108 — 8-channel output LVCMOS 1.8-V buffer
  • LMK1C1108A — 1.8V,2.5V or 3.3V asynchronous 8 channel output LVCMOS buffer
  • LMK1D1204 — 4-channel output LVDS 1.8-V buffer
  • LMK1D1204P — 4-channel output LVDS 1.8-V, 2.5-V, and 3.3-V buffer with pin control
  • LMK1D1208 — 8-channel output LVDS 1.8-V, 2.5-V, and 3.3-V buffer
  • LMK1D1208I — 8-channel output, 1.8-V, 2.5-V, and 3.3-V LVDS buffer with I²C
  • LMK1D1208P — 8-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer with pin control
  • LMK1D1212 — 12-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer
  • LMK1D1216 — 16-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer
  • LMK1D2102 — Dual bank 2-channel output LVDS 1.8-V, 2.5-V, and 3.3-V buffer
  • LMK1D2102L — Low additive jitter LVDS buffer
  • LMK1D2104 — Dual bank 4-channel output 1.8V, 2.5V and 3.3V LVDS buffer
  • LMK1D2104L — Dual bank 4-channel output LVDS 1.8V, 2.5V, and 3.3V buffer with 0.7V output common mode option
  • LMK1D2106 — Dual bank 6-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer
  • LMK1D2106L — Dual bank 2-channel output LVDS 1.8V, 2.5V and 3.3V buffer with 0.7V output common mode option
  • LMK1D2108 — Dual bank 8-channel output 1.8-V, 2.5-V, and 3.3-V LVDS buffer
Clock generators
  • LMK03318 — Ultra-low jitter clock generator family with single PLL
  • LMK03328 — Ultra-low jitter clock generator family with two independent PLLs
  • LMK03806 — Ultra-low jitter clock generator with 14 outputs
Clock jitter cleaners
  • LMK04208 — Ultra low-noise clock jitter cleaner with 6 programmable outputs
  • LMK04368-EP — Enhanced product ultra-low-noise 3.2-GHz JESD204C jitter cleaner
  • LMK04714-Q1 — Automotive, ultra low-noise 3.2-GHz, JESD204B and JESD204C dual-loop clock jitter cleaner
  • LMK04803 — Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 1.9-GHz VCO
  • LMK04805 — Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 2.2-GHz VCO
  • LMK04806 — Low-noise clock jitter cleaner with dual cascaded PLLs and integrated 2.5-GHz VCO
  • LMK04808 — Low-noise clock jitter cleaner with dual loop PLLs and integrated 2.9-GHz VCO
  • LMK04816 — Three input low-noise clock jitter cleaner with dual loop PLLs
  • LMK04821 — Ultra low jitter synthesizer and jitter cleaner with JESD204B support
  • LMK04826 — Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 1840 to1970-MHz VCO0
  • LMK04828 — Ultra low-noise JESD204B compliant clock jitter cleaner with integrated 2370 to 2630-MHz VCO0.
  • LMK04828-EP — Ultra low-noise JESD204B compliant clock jitter cleaner with temperature range -55 to 105c
  • LMK04832 — Ultra-low-noise, 3.2-GHz, 15-output, JESD204B clock jitter cleaner with dual loop
  • LMK04832-SEP — Radiation-tolerant, 30-krad, ultra-low-noise, 3.2-GHz 15-output JESD204C clock jitter cleaner
  • LMK04832-SP — Radiation-hardened-assured (RHA), ultra-low-noise, 3.2-GHz, 15-output clock jitter cleaner
  • LMK04906 — Ultra low noise clock jitter cleaner/multiplier with 6 programmable outputs
Clock network synchronizers
  • LMK05028 — Low-jitter dual-channel network synchronizer clock
  • LMK05318 — Ultra-low jitter single channel network synchronizer clock with BAW
  • LMK05318B — Ultra-low jitter single channel network synchronizer clock with BAW
  • LMK05318B-Q1 — Automotive ultra-low jitter network synchronizer and clock generator
  • LMK5B33216 — 16-output, three DPLL and APLL, network synchronizer with integrated 2.5-GHz bulk-acoustic-wave VCO
  • LMK5B33414 — 14-output, three DPLL and APLL, network synchronizer with integrated 2.5-GHz bulk-acoustic-wave VCO
  • LMK5C33216 — Ultra-low jitter clock synchronizer with JESD204B for wireless communications with BAW
  • LMK5C33216A — Three DPLL, three APLL, two-input and 16-output network synchronizer with JESD204B/C and BAW VCO
RF PLLs & synthesizers
  • LMX1204 — 12.8-GHz RF buffer, multiplier and divider with JESD204B/C SYSREF support and phase synchronization
  • LMX1214 — 1:5 18GHz RF buffer and divider with auxiliary clock
  • LMX1906-SP — Radiation-hardness-assured (RHA) 15GHz buffer, multiplier and divider with SYSREF and FPGA clock
  • LMX2430 — 3.0-GHz/0.8-GHz PLLatinum dual high frequency synthesizer for RF personal communications
  • LMX2433 — 3.6-GHz/1.7-GHz PLLatinum dual high frequency synthesizer for RF personal communications
  • LMX2434 — 5.0-GHz/2.5-GHz PLLatinum low power dual frequency synthesizer for RF personal communications
  • LMX2470 — 2.6-GHz delta-sigma fractional-N PLL with 800-MHz integer-N PLL
  • LMX2485 — 500-MHz to 3-GHz delta-sigma low power dual PLL for RF personal communications
  • LMX2485E — 50-MHz to 3-GHz delta-sigma low power dual PLL for RF personal communications
  • LMX2485Q-Q1 — 500MHz to 3GHz automotive delta-sigma low power dual PLL
  • LMX2486 — 1-GHz to 4.5-GHz delta-sigma low power dual PLL for RF personal communications
  • LMX2487 — 1 to 6-GHz delta-sigma low power dual PLLatinum frequency synthesizer with 3.0-GHz integer PLL
  • LMX2487E — 3-GHz to 7.5-GHz delta-sigma low power dual PLL for RF personal communications
  • LMX2491 — 6.4-GHz low noise fractional-N PLL with ramp/chirp generation
  • LMX2492 — 500MHz to 14GHz wideband, low noise fractional-N PLL with ramp/chirp generation
  • LMX2492-Q1 — Automotive grade 500-MHz to 14-GHz wideband, low noise fractional-N PLL with ramp/chirp generation
  • LMX2531 — High performance frequency synthesizer system with integrated VCO
  • LMX2541 — Ultra-low noise PLLatinum frequency synthesizer with integrated VCO
  • LMX2571 — 1.34-GHz, low-power, extreme-temperature RF synthesizer with frequency-shift keying (FSK) modulation
  • LMX2571-EP — Enhanced-product, 1.34-GHz, low-power, extreme-temperature RF synthesizer with FSK modulation
  • LMX2572 — 6.4-GHz low-power wideband RF synthesizer
  • LMX2572LP — 2-GHz low power wideband RF synthesizer with FSK modulation
  • LMX2581 — 3.76-GHz wideband frequency synthesizer with integrated VCO
  • LMX2581E — 3.8-GHz wideband frequency synthesizer with integrated VCO
  • LMX2582 — 5.5-GHz high performance, wideband PLLatinum RF synthesizer
  • LMX2592 — 9.8-GHz wideband frequency synthesizer with integrated VCO
  • LMX2594 — 15-GHz wideband PLLatinum™ RF synthesizer with phase synchronization and JESD204B support
  • LMX2595 — 20-GHz wideband RF synthesizer with phase synchronization & JESD204B support
  • LMX2615-SP — Space grade 40-MHz to 15-GHz wideband synthesizer with phase synchronization and JESD204B support
  • LMX2694-EP — Enhanced product 15-GHz RF synthesizer with phase synchronization
  • TRF3765 — 300M-4800MHz Low Noise Integer-N/Fractional-N PLL with Integrated VCO and up to 8 Outputs
IQ demodulators
  • LMX8410L — High-Performance Mixer With Integrated Synthesizer
Hardware development
Evaluation board
  • LMK04832EVM — LMK04832 JESD204B Clock Jitter Cleaner/Clock Generator/Distribution Evaluation Module
  • LMX2571EPEVM — LMX2571-EP evaluation module for 1.34-GHz, low-power, extreme-temperature RF synthesizer
  • LMX2594PSEVM — LMX2594 evaluation module for 15-GHz RF synthesizer with multiple-device phase synchronization
  • XMICR-3P-LMX2492 — LMX2492 X-MWblock evaluation modules
  • XMICR-3P-LMX2572 — LMX2572 X-MWblock evaluation modules
  • XMICR-3P-LMX2592 — LMX2592 X-MWblock evaluation modules
  • XMICR-3P-LMX2594 — LMX2594 X-MWblock evaluation modules
  • XMICR-3P-LMX2595 — LMX2595 X-MWblock evaluation modules
Software
Application software & framework
  • TICSPRO-SW — Texas Instruments Clocks and Synthesizers (TICS) Pro Software
IDE, configuration, compiler or debugger
  • CODELOADER — CodeLoader Software for device register programming
Support software
  • LMX9830-SW — LMX9830 Application Notes, Software, and Tools
  • LMX9838-SW — LMX9838 Application Notes, Software, and Tools
Download options
Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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