LMK6B
9.3fs ultra-low jitter, high performance, fixed frequency differential oscillator
LMK6B
- Industry’s lowest jitter:
- 9.3fs typical differential RMS jitter at 625MHz HS-LVDS with 4MHz 1st order high-pass filter (12kHz to 20MHz)
- 19.7fs typical differential RMS jitter at 312.5MHz AC-LVPECL with 4MHz 1st order high-pass filter (12kHz to 20MHz)
- 16fs typical RMS jitter at 2500MHz AC-LVPECL output (12kHz to 20MHz)
- 18fs typical, 35fs max RMS jitter at 625MHz AC-LVPECL output (12kHz to 20MHz)
- 28fs typical RMS jitter at 312.5MHz AC-LVPECL output (12kHz to 20MHz)
- Exceptional PSRR performance (ripple frequencies > 10kHz, 50mV supply ripple, 0.1µF decoupling capacitor):
- < -95dBc spurs for 156.25MHz LP-HCSL
- < -80dBc spurs for 312.5MHz LVDS
- Output frequency:
- Initial frequency offerings: 100, 125, 156.25, 312.5, 625, 1250, 2500MHz, and others
- Preview, contact TI: 322.265625, 390.625, 425, 496, 603.2291, 804.305467, 2343.75, 2400, 2412.91636, 2457.6, 2480, 2550, 2578.125MHz
- Other fixed frequencies on request
- Supports PCIe Gen 1 to Gen 7
- Output formats:
- LVDS, HS-LVDS, AC-LVPECL, Custom Swing: 50MHz to 2500MHz
- LP-HCSL: 50MHz to 625MHz
- ±25ppm total frequency stability (inclusive of all factors with 10-year aging at 25°C board temperature)
- ±7ppm temperature variation (-40°C to 105°C)
- Preview, contact TI: ±20ppm total frequency stability (inclusive of all factors with 10-year aging at 85°C board temperature)
- 91mA maximum current consumption (AC-LVPECL, Custom Swing, LVDS, HS-LVDS)
- 85mA maximum current consumption (LP-HCSL)
- 2.5V / 3.3V power supply (2.375V through 3.465V)
- Industry standard 6-pin package:
- 2.0mm × 1.6mm (wettable flank)
- Preview, contact TI: 2.5mm × 2.0mm, 3.2mm × 2.5mm
- -40°C to 105°C PCB temperature
The LMK6Bx device is an ultra-low jitter, fixed frequency oscillator achieving 9.3fs at 625MHz. This device incorporates the BAW as the resonator source. The device is factory programmed per specific operation mode, including frequency, output type, function pin, and frequency stability.
The high-performance clocking, mechanical stability, flexibility, and small package options for this device are designed for reference and core clocks in high-speed SerDes used in telecommunications, data and enterprise network, and industrial applications.
Technical documentation
| Top documentation | Type | Title | Format options | Date |
|---|---|---|---|---|
| * | Data sheet | LMK6B 9.3fs Ultra-Low Jitter, High-performance Differential Oscillator datasheet | PDF | HTML | 10 Mar 2026 |
| Application note | Clocking LMK6Bx with TI Clock Buffers | PDF | HTML | 11 Mar 2026 | |
| Application note | The LMK6B: Revolutionizing Optical Module Performance with Industry-Leading Ultra-Low Jitter BAW Oscillators | PDF | HTML | 11 Mar 2026 | |
| EVM User's guide | LMK6B Evaluation Module | PDF | HTML | 09 Mar 2026 |
Design & development
For additional terms or required resources, click any title below to view the detail page where available.
PLLATINUMSIM-SW — PLL loop filter, phase noise, lock time, and spur simulation tool
PLLATINUMSIM-SW is a simulation tool that allows users to create detailed designs and simulations of our PLLatinum™ integrated circuits, which include the LMX series of phase-locked loops (PLLs) and synthesizers.
Supported products & hardware
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
| Package | Pins | CAD symbols, footprints & 3D models |
|---|---|---|
| VSON (DLR) | 6 | Ultra Librarian |
Ordering & quality
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- MSL rating/Peak reflow
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- Ongoing reliability monitoring
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Support & training
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