LMK5B12212EVM
LMK5B12212 评估模块
LMK5B12212EVM
概述
LMK5B12212 评估模块 (EVM) 用于评估 LMK5B12212 网络时钟发生器和同步器。该 EVM 可用于器件评估、合规性测试和系统原型设计。 LMK5B12212 集成了三个模拟 PLL (APLL) 和三个具有可编程环路带宽的数字 PLL (DPLL)。该 EVM 包含针对时钟输入、振荡器输入和时钟输出的 SMA 连接器,以便将器件连接到 50Ω 测试设备。通过板载 TCXO,可在自由运行、锁定或保持模式下评估 LMK5B12212。通过板载 USB 微控制器 (MCU) 接口,可在 PC 上使用 TICS Pro 软件图形用户界面 (GUI) 来配置该 EVM。TICS Pro 可用于对 LMK5B12212 寄存器进行编程。
特性
- 一个具有可编程带宽的数字 PLL (DPLL) 和两个分数模拟 PLL (APLL),可实现灵活的时钟生成
- DPLL 有两个基准输入,可支持无中断切换和保持
- 12 路输出时钟: 由 BAW 驱动的输出可实现低于 50fs 的 RMS 相位抖动(12kHz 至 20MHz)
- 灵活的振荡器源:板载 TCXO,或其他 XO、TCXO、OCXO 的几种类型之一,或外部 SMA 输入选项
- 通过片上 EEPROM 来存储自定义的启动时钟配置
- 3 英尺 Mini-USB 电缆 (MPN 3021003-03)
时钟网络同步器
立即订购并开发
LMK5B12212EVM — LMK5B12212 evaluation module
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
TICS Pro 1.7.7.9 installer binary for Windows operating system
产品
时钟发生器
时钟缓冲器
Oscillators
时钟抖动清除器
时钟网络同步器
射频 PLL 与合成器
硬件开发
评估板
文档
TICS Pro 1.7.7.9 Release Notes
TICS Pro 1.7.7.9 Software Manifest
发布信息
NOTE: v1.7.7.8 was withdrawn due to the installer being built with an older version of several profiles. v1.7.7.9 includes the correct files, and is otherwise identical to v1.7.7.8.
Bug Fixes
- Start Page: dimming improvements for unused input references, force FB config 1 only and require manual copying for FB config 2
- Validation Page: DPLL LOFL validation registers for FB2 are programmed for cases where FB2 is used
- ZDM Page: Added relative time calculations for DPLLx_PH_OFFSET
- Programming Page: Added DPLL loop filter register generator, clearly indicate ROM-only registers for post-EEPROM boot sequence
- LMK5B12212 will now calculate loop filter values
- LMK5B12212 and LMK5C12212A "Read Status" and "Read RO Regs" buttons fixed
- LMK5B12212 and LMK5C12212A corrected PLL1 VCO post-divider frequency on OUT0&1, OUT2&3 pages
- Improved accuracy of frequency error warnings
- Frequency Planner: OUT0/OUT1 CMOS and LDO voltage are now correctly set, REFx for OUT0 or OUT1 is now correctly set
- ZDM configuration now fails more gracefully for unsupported non-integer input/output attempts
Known Issues
- NEW: LMK5B and LMK5C family - In some cases, "Assign Selected VCO Settings to Device" and "Apply Output Clock Settings to Device" may need to be pressed twice for certain cascaded configurations to display correctly
- LMK5C33216 - When cascading from VCO3 to DPLL input, the divide value must manually be entered into DPLLx_REF5_RDIV as ( VCO3 output frequency / DPLLx TDC frequency )
- LMK05318 - In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
- Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
- User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.
技术文档
类型 | 标题 | 下载最新的英文版本 | 日期 | |||
---|---|---|---|---|---|---|
证书 | LMK5B12212EVM EU Declaration of Conformity (DoC) | 2023年 9月 29日 |