LMX1204EVM
适用于 LMX1204 支持 JESD204B/C SYSREF 的射频缓冲器、乘法器和分频器的评估模块
LMX1204EVM
概述
LMX1204 评估模块 (EVM) 旨在评估 LMX1204 的性能,后者是一款四输出、超低附加抖动射频缓冲器、分频器和乘法器。该 EVM 可以缓冲高达 12.8GHz 的射频时钟输入,在 3.2GHz 至 6.4GHz 的输出范围内乘以 x2、x3 或 x4,并对输入进行最高 8 分频。
包含用于现场可编程门阵列 (FPGA) 和逻辑时钟的独立型辅助时钟分频器,每个输出都包括一个具有皮秒精度和延迟调优能力的系统参考 (SYSREF) 补偿。多个器件可以同步以实现宽时钟分配树。
特性
- 12.8GHz 缓冲器,高达 6.4GHz 的乘法器和最高 8 分频
- -6GHz 时具有 -160dBc/Hz 本底噪声
- 四射频输出和 SYSREF 对
- 具有每输出皮秒精度延迟调优能力的 SYSREF 发生器
- 用于 FPGA 和逻辑的辅助分频器,具有 SYSREF
- 支持多器件同步
- USB-A 转 USB-B Micro 电缆
射频 PLL 与合成器
开始使用
- 订购 LMX1204EVM
- 下载并安装 TICSPRO-SW 和 PLLATINUMSIM-SW
- 阅读 LMX1204EVM 用户指南
- 在 TICSPRO-SW 上配置寄存器并在 PLLATINUMSIM-SW 上仿真性能
立即订购并开发
LMX1204EVM — 适用于 LMX1204 支持 JESD204B/C SYSREF 的射频缓冲器、乘法器和分频器的评估模块
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
TICS Pro 1.7.7.9 installer binary for Windows operating system
产品
时钟发生器
时钟缓冲器
Oscillators
时钟抖动清除器
时钟网络同步器
射频 PLL 与合成器
硬件开发
评估板
文档
TICS Pro 1.7.7.9 Release Notes
TICS Pro 1.7.7.9 Software Manifest
发布信息
NOTE: v1.7.7.8 was withdrawn due to the installer being built with an older version of several profiles. v1.7.7.9 includes the correct files, and is otherwise identical to v1.7.7.8.
Bug Fixes
- Start Page: dimming improvements for unused input references, force FB config 1 only and require manual copying for FB config 2
- Validation Page: DPLL LOFL validation registers for FB2 are programmed for cases where FB2 is used
- ZDM Page: Added relative time calculations for DPLLx_PH_OFFSET
- Programming Page: Added DPLL loop filter register generator, clearly indicate ROM-only registers for post-EEPROM boot sequence
- LMK5B12212 will now calculate loop filter values
- LMK5B12212 and LMK5C12212A "Read Status" and "Read RO Regs" buttons fixed
- LMK5B12212 and LMK5C12212A corrected PLL1 VCO post-divider frequency on OUT0&1, OUT2&3 pages
- Improved accuracy of frequency error warnings
- Frequency Planner: OUT0/OUT1 CMOS and LDO voltage are now correctly set, REFx for OUT0 or OUT1 is now correctly set
- ZDM configuration now fails more gracefully for unsupported non-integer input/output attempts
Known Issues
- NEW: LMK5B and LMK5C family - In some cases, "Assign Selected VCO Settings to Device" and "Apply Output Clock Settings to Device" may need to be pressed twice for certain cascaded configurations to display correctly
- LMK5C33216 - When cascading from VCO3 to DPLL input, the divide value must manually be entered into DPLLx_REF5_RDIV as ( VCO3 output frequency / DPLLx TDC frequency )
- LMK05318 - In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
- Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
- User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.
技术文档
类型 | 标题 | 下载最新的英文版本 | 日期 | |||
---|---|---|---|---|---|---|
* | EVM 用户指南 | LMX1204EVM User's Guide (Rev. A) | PDF | HTML | 2022年 8月 11日 | ||
证书 | LMX1204EVM EU RoHS Declaration of Conformity (DoC) | 2021年 8月 11日 |