LMX2581EVM
LMX2581 评估模块
LMX2581EVM
概述
LMX2581 宽带频率合成器可生成各种频率,且相位噪声极低。LMX2581 参考板 (LMX2581EVM) 旨在帮助评估系统中的 LMX2581,同时充当客户系统的参考设计。除参考板套件外,只需一台 PC 和相位噪声分析器即可使用。该评估板可通过 CodeLoader 进行评估和控制,并且 CodeLoader 是为与该板配套使用而开发的。CodeLoader 软件能对该器件进行全面控制,同时还能够由 Active X 通过程序(如 Excel 和 Labview)进行调用。该板的功能就是能获得极大的灵活性和便利性。默认配置有一个 XO 且附有两路差分输出。但是,元件可进行更换,从而使外部信号发生器能进行此操作。除此之外,外部 VCO 也可添加无源或有源环路滤波器。
特性
- 指示锁定情况的 LED
- 板载外部 VCO 或外部振荡器输入的调节
- 通过 USB 的串行控制
开始使用
- 订购 LMX2581EVM
- 下载并安装 TICSPRO-SW 和 PLLATINUMSIM-SW
- 阅读 LMX2581EVM 用户指南
- 在 TICSPRO-SW 上配置寄存器并在 PLLATINUMSIM-SW 上仿真性能
立即订购并开发
LMX2581EVM — LMX2581 评估模块
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
TICS Pro 1.7.7.9 installer binary for Windows operating system
产品
时钟发生器
时钟缓冲器
振荡器
时钟抖动清除器
时钟网络同步器
射频 PLL 与合成器
硬件开发
评估板
文档
TICS Pro 1.7.7.9 Release Notes
TICS Pro 1.7.7.9 Software Manifest
发布信息
NOTE: v1.7.7.8 was withdrawn due to the installer being built with an older version of several profiles. v1.7.7.9 includes the correct files, and is otherwise identical to v1.7.7.8.
Bug Fixes
- Start Page: dimming improvements for unused input references, force FB config 1 only and require manual copying for FB config 2
- Validation Page: DPLL LOFL validation registers for FB2 are programmed for cases where FB2 is used
- ZDM Page: Added relative time calculations for DPLLx_PH_OFFSET
- Programming Page: Added DPLL loop filter register generator, clearly indicate ROM-only registers for post-EEPROM boot sequence
- LMK5B12212 will now calculate loop filter values
- LMK5B12212 and LMK5C12212A "Read Status" and "Read RO Regs" buttons fixed
- LMK5B12212 and LMK5C12212A corrected PLL1 VCO post-divider frequency on OUT0&1, OUT2&3 pages
- Improved accuracy of frequency error warnings
- Frequency Planner: OUT0/OUT1 CMOS and LDO voltage are now correctly set, REFx for OUT0 or OUT1 is now correctly set
- ZDM configuration now fails more gracefully for unsupported non-integer input/output attempts
Known Issues
- NEW: LMK5B and LMK5C family - In some cases, "Assign Selected VCO Settings to Device" and "Apply Output Clock Settings to Device" may need to be pressed twice for certain cascaded configurations to display correctly
- LMK5C33216 - When cascading from VCO3 to DPLL input, the divide value must manually be entered into DPLLx_REF5_RDIV as ( VCO3 output frequency / DPLLx TDC frequency )
- LMK05318 - In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
- Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
- User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.
技术文档
类型 | 标题 | 下载最新的英文版本 | 日期 | |||
---|---|---|---|---|---|---|
证书 | LMX2581EVM EU Declaration of Conformity (DoC) | 2019年 1月 2日 | ||||
数据表 | LMX2581 具有集成 VCO 的宽带频率合成器 数据表 (Rev. G) | PDF | HTML | 英语版 (Rev.G) | PDF | HTML | 2015年 2月 10日 | |
EVM 用户指南 | LMX2581EVM User's Guide (Rev. C) | 2013年 11月 25日 |