LMK04828BEVM
LMK04828 评估模块
LMK04828BEVM
概述
LMK04828BEVM 和 LMK04826BEVM 评估模块 (EVM) 支持 LMK0482x 系列器件。LMK0482x 器件是支持 JEDEC JESD204B 且在业内具有超高性能的时钟调节器。PLLATINUM™ 集成电路的双环路架构使用低噪声 VCXO 模块实现低于 100fs 的抖动 (12kHz 至 20MHz)。双环路架构由两个高性能锁相环 (PLL)、一个低噪声晶体振荡器电路以及一个高性能压控振荡器 (VCO) 构成。
第一个 PLL (PLL1) 提供低噪声抖动消除器功能。第二个 PLL (PLL2) 执行时钟和 SYSREF 生成。PLL1 可配置为与外部 VCXO 模块配合使用,或与具有外部可调晶体和变容二极管的集成式晶体振荡器配合使用。用于很窄的环路带宽时,PLL1 使用 VCXO 模块或可调晶体的优异近端相位噪声(偏移低于 50kHz)清理输入时钟。PLL1 的输出将用作 PLL2 的清理输入参考,以锁定集成式 VCO。
可对 PLL2 的环路带宽进行优化以清理远端相位噪声(偏移高于 50 kHz),集成式 VCO 优于 VCXO 模块或 PLL1 中使用的可调晶体。
特性
- JEDEC JESD204B 支持
- 超低的 rms 抖动
- 双环路架构
- 3 个带有 LOS 的冗余输入时钟
- 精密数字延迟,固定或动态可调
时钟抖动清除器
开始使用
- 订购 LMK04828BEVM
- 下载并安装 TICSPRO-SW 和 PLLATINUMSIM-SW
- 阅读 LMK04828BEVM 用户指南
- 在 TICSPRO-SW 上配置寄存器并在 PLLATINUMSIM-SW 上仿真性能
立即订购并开发
LMK04828BEVM — LMK04828 评估模块
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
TICS Pro 1.7.7.9 installer binary for Windows operating system
产品
时钟发生器
时钟缓冲器
Oscillators
时钟抖动清除器
时钟网络同步器
射频 PLL 与合成器
硬件开发
评估板
文档
TICS Pro 1.7.7.9 Release Notes
TICS Pro 1.7.7.9 Software Manifest
发布信息
NOTE: v1.7.7.8 was withdrawn due to the installer being built with an older version of several profiles. v1.7.7.9 includes the correct files, and is otherwise identical to v1.7.7.8.
Bug Fixes
- Start Page: dimming improvements for unused input references, force FB config 1 only and require manual copying for FB config 2
- Validation Page: DPLL LOFL validation registers for FB2 are programmed for cases where FB2 is used
- ZDM Page: Added relative time calculations for DPLLx_PH_OFFSET
- Programming Page: Added DPLL loop filter register generator, clearly indicate ROM-only registers for post-EEPROM boot sequence
- LMK5B12212 will now calculate loop filter values
- LMK5B12212 and LMK5C12212A "Read Status" and "Read RO Regs" buttons fixed
- LMK5B12212 and LMK5C12212A corrected PLL1 VCO post-divider frequency on OUT0&1, OUT2&3 pages
- Improved accuracy of frequency error warnings
- Frequency Planner: OUT0/OUT1 CMOS and LDO voltage are now correctly set, REFx for OUT0 or OUT1 is now correctly set
- ZDM configuration now fails more gracefully for unsupported non-integer input/output attempts
Known Issues
- NEW: LMK5B and LMK5C family - In some cases, "Assign Selected VCO Settings to Device" and "Apply Output Clock Settings to Device" may need to be pressed twice for certain cascaded configurations to display correctly
- LMK5C33216 - When cascading from VCO3 to DPLL input, the divide value must manually be entered into DPLLx_REF5_RDIV as ( VCO3 output frequency / DPLLx TDC frequency )
- LMK05318 - In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
- Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
- User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.
技术文档
类型 | 标题 | 下载最新的英文版本 | 日期 | |||
---|---|---|---|---|---|---|
* | 用户指南 | LMK04826/28 User’s Guide (Rev. B) | 2018年 3月 13日 | |||
证书 | LMK04828BEVM EU Declaration of Conformity (DoC) | 2019年 1月 2日 | ||||
数据表 | LMK0482x Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner With Dual Loop PLLs 数据表 (Rev. AS) | PDF | HTML | 2017年 9月 27日 |