LMX2572EVM
具有相位同步功能且支持 JESD204B 的 6.4GHz 低功耗宽带射频合成器
LMX2572EVM
概述
此评估模块适用于 LMX2572,该器件是一个低功耗、高性能的宽带合成器,可生成 13MHz 到 6.4GHz 的任何频率,而无需使用内部倍频器。该 PLL 可提供优异的性能,而 3.3V 单电源中的电流消耗仅为 75mA。此器件支持 JESD204B 标准(它可以生成或重复 SYSREF 信号),是测量高速数据转换器速度的理想之选。通过提供 SYNC 信号,用户可以跨多个 LMX2572 器件同步输出相位。LMX2572 还可以生成频率斜升,并可将其在此评估模块进行演示。此外,LMX2572 还支持直接数字 FSK 调制。为此,可以将串行接口配置为 SPI 或 I2S 接口。可使用配套的 Refernce Pro 模块来提供干净的参考时钟以及对 LMX2572 评估模块进行编程。
特性
- 13MHz 至 6.4GHz 输出频率
- 在 100KHz 偏移和 6.4GHz 载波的情况下具有 -106dBc/Hz 的相位噪声
- 75mA 工作电流及一个直接 VCO 输出
- 两路差动输出,具有可编程的输出功率
- 此 EVM 具有用于合成器的完整电路,经过性能优化和测试,并包括一个 USB 编程模块
射频 PLL 与合成器
开始使用
- 订购 LMX2572EVM
- 下载并安装 TICSPRO-SW 和 PLLATINUMSIM-SW
- 阅读 LMX2572EVM 用户指南
- 在 TICSPRO-SW 上配置寄存器并在 PLLATINUMSIM-SW 上仿真性能
立即订购并开发
LMX2572EVM — 具有相位同步功能且支持 JESD204B 的 6.4GHz 低功耗宽带射频合成器
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
TICS Pro 1.7.7.9 installer binary for Windows operating system
产品
时钟发生器
时钟缓冲器
Oscillators
时钟抖动清除器
时钟网络同步器
射频 PLL 与合成器
硬件开发
评估板
文档
TICS Pro 1.7.7.9 Release Notes
TICS Pro 1.7.7.9 Software Manifest
发布信息
NOTE: v1.7.7.8 was withdrawn due to the installer being built with an older version of several profiles. v1.7.7.9 includes the correct files, and is otherwise identical to v1.7.7.8.
Bug Fixes
- Start Page: dimming improvements for unused input references, force FB config 1 only and require manual copying for FB config 2
- Validation Page: DPLL LOFL validation registers for FB2 are programmed for cases where FB2 is used
- ZDM Page: Added relative time calculations for DPLLx_PH_OFFSET
- Programming Page: Added DPLL loop filter register generator, clearly indicate ROM-only registers for post-EEPROM boot sequence
- LMK5B12212 will now calculate loop filter values
- LMK5B12212 and LMK5C12212A "Read Status" and "Read RO Regs" buttons fixed
- LMK5B12212 and LMK5C12212A corrected PLL1 VCO post-divider frequency on OUT0&1, OUT2&3 pages
- Improved accuracy of frequency error warnings
- Frequency Planner: OUT0/OUT1 CMOS and LDO voltage are now correctly set, REFx for OUT0 or OUT1 is now correctly set
- ZDM configuration now fails more gracefully for unsupported non-integer input/output attempts
Known Issues
- NEW: LMK5B and LMK5C family - In some cases, "Assign Selected VCO Settings to Device" and "Apply Output Clock Settings to Device" may need to be pressed twice for certain cascaded configurations to display correctly
- LMK5C33216 - When cascading from VCO3 to DPLL input, the divide value must manually be entered into DPLLx_REF5_RDIV as ( VCO3 output frequency / DPLLx TDC frequency )
- LMK05318 - In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
- Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
- User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.
技术文档
类型 | 标题 | 下载最新的英文版本 | 日期 | |||
---|---|---|---|---|---|---|
* | EVM 用户指南 | LMX2572EVM Evaluation Instructions (Rev. B) | 2019年 7月 19日 | |||
数据表 | 具有相位同步功能和 JESD204B 支持的 LMX2572 6.4GHz 低功耗宽带射频合成器 数据表 (Rev. B) | PDF | HTML | 英语版 (Rev.B) | PDF | HTML | 2019年 3月 11日 | |
证书 | LMX2572EVM EU Declaration of Conformity (DoC) | 2019年 1月 2日 |