LMK61E2EVM
LMK61E2EVM 超低抖动可编程振荡器评估模块
LMK61E2EVM
概述
LMK61E2EVM 评估模块提供了一个完整平台来评估具有集成式 EEPROM 和频率容限功能的德州仪器 (TI) LMK61E2 超低抖动可编程差动振荡器的 90fs RMS 抖动性能和可配置性。
LMK61E2EVM 可以用作抖动关键型应用的高性能时钟源,且可以轻松定制为用户期望的任何频率和输出格式。借助板载的 USB 转 I2C 接口,可通过软件图形用户界面 (GUI) 进行器件配置,且无需提供外部输入或电源即可运行器件。边缘发射 SMA 端口可用于访问 LMK61E2 的差分时钟输出,从而使用市售同轴电缆、适配器或平衡-非平衡变压器(未附带)连接到测试设备或参考板。
特性
- 超低抖动差分时钟生成
- 通过 USB 或从外部供电(SMA 连接器)
- 板载的 USB 转 I2C 接口
- 粗细频率容限
- 通过 GUI 平台全面访问 LMK03328 寄存器和 EEPROM
- LMK61E2EVM
- 3-ft. USB cable, Q362-ND
立即订购并开发
LMK61E2EVM — LMK61E2EVM 超低抖动可编程振荡器评估模块
SNAC074 — LMK61xx Oscillator Programming Tool
SNAC074 — LMK61xx Oscillator Programming Tool
产品
Oscillators
硬件开发
评估板
发布信息
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
TICS Pro 1.7.7.9 installer binary for Windows operating system
产品
时钟发生器
时钟缓冲器
Oscillators
时钟抖动清除器
时钟网络同步器
射频 PLL 与合成器
硬件开发
评估板
文档
TICS Pro 1.7.7.9 Release Notes
TICS Pro 1.7.7.9 Software Manifest
发布信息
NOTE: v1.7.7.8 was withdrawn due to the installer being built with an older version of several profiles. v1.7.7.9 includes the correct files, and is otherwise identical to v1.7.7.8.
Bug Fixes
- Start Page: dimming improvements for unused input references, force FB config 1 only and require manual copying for FB config 2
- Validation Page: DPLL LOFL validation registers for FB2 are programmed for cases where FB2 is used
- ZDM Page: Added relative time calculations for DPLLx_PH_OFFSET
- Programming Page: Added DPLL loop filter register generator, clearly indicate ROM-only registers for post-EEPROM boot sequence
- LMK5B12212 will now calculate loop filter values
- LMK5B12212 and LMK5C12212A "Read Status" and "Read RO Regs" buttons fixed
- LMK5B12212 and LMK5C12212A corrected PLL1 VCO post-divider frequency on OUT0&1, OUT2&3 pages
- Improved accuracy of frequency error warnings
- Frequency Planner: OUT0/OUT1 CMOS and LDO voltage are now correctly set, REFx for OUT0 or OUT1 is now correctly set
- ZDM configuration now fails more gracefully for unsupported non-integer input/output attempts
Known Issues
- NEW: LMK5B and LMK5C family - In some cases, "Assign Selected VCO Settings to Device" and "Apply Output Clock Settings to Device" may need to be pressed twice for certain cascaded configurations to display correctly
- LMK5C33216 - When cascading from VCO3 to DPLL input, the divide value must manually be entered into DPLLx_REF5_RDIV as ( VCO3 output frequency / DPLLx TDC frequency )
- LMK05318 - In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
- Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
- User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.
技术文档
类型 | 标题 | 下载最新的英文版本 | 日期 | |||
---|---|---|---|---|---|---|
* | EVM 用户指南 | LMK61E2EVM, LMK61E0MEVM User's Guide (Rev. B) | 2017年 8月 10日 | |||
证书 | LMK61E2EVM EU Declaration of Conformity (DoC) | 2019年 1月 2日 | ||||
数据表 | 具有内部 EEPROM 的 LMK61E2 超低抖动可编程振荡器 数据表 (Rev. B) | PDF | HTML | 英语版 (Rev.B) | PDF | HTML | 2017年 7月 27日 | |
技术文章 | How to select an optimal clocking solution for your FPGA-based design | PDF | HTML | 2015年 12月 9日 |