LMX2592EVM
LMX2592EVM 高性能宽带频率射频合成器 PLLATINUM™ 集成电路
LMX2592EVM
概述
LMX2592EVM 评估模块 (EVM) 适用于 LMX2592 器件。LMX2592 器件能够以业内先进的相位噪声水平输出极高频率的信号。集成式压控振荡器 (VCO) 有助于尽可能减少要设计的分立式外部元件。印刷电路板 (PCB) 经过性能优化,并且设计为能够轻松定制环路滤波器。采用 LED 设计,用于快速目视检查 PLL 锁定状态。借助板载振荡器,设置过程中只需要一个 3.3V 电源和一个附带的 USB2ANY 接口适配器。此外,软件易于操作,提供直观且易用的 GUI。
特性
- 极低的 20-9800MHz 相位噪声输出
- 可锁定 5-1400MHz 输入信号
- 3.3V 单电源
- 两路差动输出,具有可编程的输出功率
- 适用于合成器的完整电路,已经过性能优化和测试,并且包含一个 USB 编程模块
- LMX2592EVM
- USB2ANY
射频 PLL 与合成器
开始使用
- 订购 LMX2592EVM
- 下载并安装 TICSPRO-SW 和 PLLATINUMSIM-SW
- 阅读 LMX2592EVM 用户指南
- 在 TICSPRO-SW 上配置寄存器并在 PLLATINUMSIM-SW 上仿真性能
立即订购并开发
LMX2592EVM — LMX2592EVM 高性能宽带频率射频合成器 PLLATINUM™ 集成电路
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
TICS Pro 1.7.7.9 installer binary for Windows operating system
产品
时钟发生器
时钟缓冲器
Oscillators
时钟抖动清除器
时钟网络同步器
射频 PLL 与合成器
硬件开发
评估板
文档
TICS Pro 1.7.7.9 Release Notes
TICS Pro 1.7.7.9 Software Manifest
发布信息
NOTE: v1.7.7.8 was withdrawn due to the installer being built with an older version of several profiles. v1.7.7.9 includes the correct files, and is otherwise identical to v1.7.7.8.
Bug Fixes
- Start Page: dimming improvements for unused input references, force FB config 1 only and require manual copying for FB config 2
- Validation Page: DPLL LOFL validation registers for FB2 are programmed for cases where FB2 is used
- ZDM Page: Added relative time calculations for DPLLx_PH_OFFSET
- Programming Page: Added DPLL loop filter register generator, clearly indicate ROM-only registers for post-EEPROM boot sequence
- LMK5B12212 will now calculate loop filter values
- LMK5B12212 and LMK5C12212A "Read Status" and "Read RO Regs" buttons fixed
- LMK5B12212 and LMK5C12212A corrected PLL1 VCO post-divider frequency on OUT0&1, OUT2&3 pages
- Improved accuracy of frequency error warnings
- Frequency Planner: OUT0/OUT1 CMOS and LDO voltage are now correctly set, REFx for OUT0 or OUT1 is now correctly set
- ZDM configuration now fails more gracefully for unsupported non-integer input/output attempts
Known Issues
- NEW: LMK5B and LMK5C family - In some cases, "Assign Selected VCO Settings to Device" and "Apply Output Clock Settings to Device" may need to be pressed twice for certain cascaded configurations to display correctly
- LMK5C33216 - When cascading from VCO3 to DPLL input, the divide value must manually be entered into DPLLx_REF5_RDIV as ( VCO3 output frequency / DPLLx TDC frequency )
- LMK05318 - In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
- Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
- User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.
技术文档
类型 | 标题 | 下载最新的英文版本 | 日期 | |||
---|---|---|---|---|---|---|
* | EVM 用户指南 | LMX2592EVM User's Guide | 2015年 12月 18日 | |||
证书 | LMX2592EVM EU Declaration of Conformity (DoC) (Rev. B) | 2024年 3月 27日 |