AM62A1-Q1

ACTIVE

Automotive processor with RGB-IR ISP, video enc/dec for 1-2 cameras, low-power systems

Product details

CPU 4 Arm Cortex-A53 Frequency (MHz) 140 Coprocessors 1 Arm Cortex-R5F Display type MIPI DPI Protocols Ethernet, TSN Hardware accelerators Deep learning accelerator, Video decode accelerator, Video encode accelerator, Vision processing accelerator Features Vision Analytics Operating system Linux, RTOS Security Secure boot TI functional safety category Functional Safety-Compliant Rating Automotive Operating temperature range (°C) -40 to 125 Edge AI enabled No
CPU 4 Arm Cortex-A53 Frequency (MHz) 140 Coprocessors 1 Arm Cortex-R5F Display type MIPI DPI Protocols Ethernet, TSN Hardware accelerators Deep learning accelerator, Video decode accelerator, Video encode accelerator, Vision processing accelerator Features Vision Analytics Operating system Linux, RTOS Security Secure boot TI functional safety category Functional Safety-Compliant Rating Automotive Operating temperature range (°C) -40 to 125 Edge AI enabled No
FCCSP (ANF) 484 324 mm² 18 x 18

Processor Cores:

  • Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated as part of MCU Channel with FFI
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
    • 512KB SRAM with SECDED ECC
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Device Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Deep Learning Accelerator based on Single-core C7x
    • C7x floating point, up to 40 GFLOPS, 256-bit Vector DSP at 1.0GHz
    • Matrix Multiply Accelerator (MMA), up to 2TOPS (8b) at 1.0GHz
    • 64KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
    • 1.25MB of L2 SRAM with SECDED ECC
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators:
    • 315MPixel/s ISP; Up to 5MP @ 60fps
    • Support for 12-bit RGB-IR
    • Support for up to 16-bit input RAW format
    • Line support up to 4096
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
      • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

Multimedia:

  • Display subsystem
    • Single display support
    • Up to 2048x1080 @ 60fps
    • Up to 165MHz pixel clock support with independent PLL
    • DPI 24-bit RGB parallel interface
    • Supports safety features such as freeze frame detection and MISR data check
  • One Camera Serial interface (CSI-2) Receiver with 4-Lane D-PHY
    • MIPI CSI-2 v1.3 Compliant + MIPI D-PHY 1.2
    • Support for 1,2,3 or 4 data lane mode up to 2.5Gbps per lane
    • ECC verification/correction with CRC check + ECC on RAM
    • Virtual Channel support (up to 16)
    • Ability to write stream data directly to DDR via DMA
  • Video Encoder/Decoder
    • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
    • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
    • Support for up to 4K UHD resolution (3840 × 2160)
      • Clocking options supporting 240MPixels/s, 120MPixels/s, or 60MPixels/s
  • Motion JPEG encode at 416MPixels/s withresolutions up to 4K UHD (3840 × 2160)

Memory Subsystem:

  • Up to 2.29MB of On-chip RAM
    • 64KB of On-Chip RAM (OCRAM) with SECDED ECC, can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
    • 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
    • 176KB of On-Chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
    • 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
    • 64KB of On-chip RAM with SECDED ECC in Device/Power Manager Subsystem
    • 1.25MB of L2 SRAM with SECDED ECC in C7x Deep Learning Accelerator
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4
    • 32-bit data bus with inline ECC
    • Supports speeds up to 3733MT/s
    • Max addressable range of 8GBytes

Functional Safety:

  • Functional Safety-Compliant targeted [Industrial]
    • Developed for functional safety applications
    • Documentation will be available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3 targeted
    • Hardware Integrity up to SIL 2 targeted
    • Safety-related certification
      • IEC 61508 by TÜV SÜD planned
  • Functional Safety-Compliant targeted [Automotive]
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL D targeted
    • Hardware integrity up to ASIL B targeted
    • Safety-related certification
      • ISO 26262 by TÜV SÜD planned
  • AEC - Q100 qualified [Automotive]

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-Speed Interfaces:

  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time Sensitive Networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • Two USB2.0 Ports
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection

General Connectivity:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 6x Inter-Integrated Circuit (I2C) ports
  • 3x Multichannel Audio Serial Ports (McASP)
    • Transmit and Receive Clocks up to 50MHz
    • Up to 4/6/16 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
    • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
    • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
    • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Support for audio reference output clock
  • 3x enhanced PWM modules (ePWM)
  • 3x enhanced Quadrature Encoder Pulse modules (eQEP)
  • 3x enhanced Capture modules (eCAP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 3x Controller Area Network (CAN) modules with CAN-FD support
    • Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1
    • Full CAN FD support (up to 64 data bytes)
    • Parity/ECC check for Message RAM
    • Speed up to 8Mbps

Media and Data Storage:

  • 3x Multi-Media Card/Secure Digital (MMC/SD/SDIO) interface
    • 1x 8-bit eMMC interface up to HS200 speed
    • 2x 4-bit SD/SDIO interface up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133MHz
    • Flexible 8- and 16-bit Asynchronous Memory Interface with up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
    • Uses BCH code to support 4-, 8-, or 16-bit ECC
    • Uses Hamming code to support 1-bit ECC
    • Error Locator Module (ELM)
      • Used with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
      • Supports 4-, 8-, and 16-bit per 512-Byte block error location based on BCH algorithms
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR Flash devices
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Power Management:

  • Low-power modes supported by Device/Power Manager
    • Partial IO support for CAN/GPIO/UART wakeup
    • DeepSleep : I/O + DDR (suspend to RAM)
    • DeepSleep
    • MCU Only
    • Standby
    • Dynamic frequency scaling for Cortex-A53

Boot Options:

  • UART
  • I2C EEPROM
  • OSPI/QSPI Flash
  • GPMC NOR/NAND Flash
  • Serial NAND Flash
  • SD Card
  • eMMC
  • USB (host) boot from Mass Storage device
  • USB (device) boot from external host (DFU mode)
  • Ethernet

Technology / Package:

  • 16-nm FinFET technology
  • 18mm x 18mm, 0.8mm pitch full-array, 484-pin FCBGA (AMB)
  • 18mm x 18mm, 0.8mm pitch full-array, 484-pin FCCSP (ANF)

Processor Cores:

  • Up to Quad 64-bit Arm Cortex-A53 microprocessor subsystem at up to 1.4GHz
    • Quad-core Cortex-A53 cluster with 512KB L2 shared cache with SECDED ECC
    • Each A53 core has 32KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated as part of MCU Channel with FFI
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
    • 512KB SRAM with SECDED ECC
  • Single-core Arm Cortex-R5F at up to 800MHz, integrated to support Device Management
    • 32KB ICache, 32KB L1 DCache, and 64KB TCM with SECDED ECC on all memories
  • Deep Learning Accelerator based on Single-core C7x
    • C7x floating point, up to 40 GFLOPS, 256-bit Vector DSP at 1.0GHz
    • Matrix Multiply Accelerator (MMA), up to 2TOPS (8b) at 1.0GHz
    • 64KB L1 DCache with SECDED ECC and 32KB L1 ICache with Parity protection
    • 1.25MB of L2 SRAM with SECDED ECC
  • Vision Processing Accelerators (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators:
    • 315MPixel/s ISP; Up to 5MP @ 60fps
    • Support for 12-bit RGB-IR
    • Support for up to 16-bit input RAW format
    • Line support up to 4096
    • Wide Dynamic Range (WDR), Lens Distortion Correction (LDC), Vision Imaging Subsystem (VISS), and Multi-Scalar (MSC) support
      • Output color format : 8-bits, 12-bits, and YUV 4:2:2, YUV 4:2:0, RGB, HSV/HSL

Multimedia:

  • Display subsystem
    • Single display support
    • Up to 2048x1080 @ 60fps
    • Up to 165MHz pixel clock support with independent PLL
    • DPI 24-bit RGB parallel interface
    • Supports safety features such as freeze frame detection and MISR data check
  • One Camera Serial interface (CSI-2) Receiver with 4-Lane D-PHY
    • MIPI CSI-2 v1.3 Compliant + MIPI D-PHY 1.2
    • Support for 1,2,3 or 4 data lane mode up to 2.5Gbps per lane
    • ECC verification/correction with CRC check + ECC on RAM
    • Virtual Channel support (up to 16)
    • Ability to write stream data directly to DDR via DMA
  • Video Encoder/Decoder
    • Support for HEVC (H.265) Main profiles at Level 5.1 High-tier
    • Support for H.264 BaseLine/Main/High Profiles at Level 5.2
    • Support for up to 4K UHD resolution (3840 × 2160)
      • Clocking options supporting 240MPixels/s, 120MPixels/s, or 60MPixels/s
  • Motion JPEG encode at 416MPixels/s withresolutions up to 4K UHD (3840 × 2160)

Memory Subsystem:

  • Up to 2.29MB of On-chip RAM
    • 64KB of On-Chip RAM (OCRAM) with SECDED ECC, can be divided into smaller banks in increments of 32KB for as many as 2 separate memory banks
    • 256KB of On-Chip RAM with SECDED ECC in SMS Subsystem
    • 176KB of On-Chip RAM with SECDED ECC in SMS Subsystem for TI security firmware
    • 512KB of On-chip RAM with SECDED ECC in Cortex-R5F MCU Subsystem
    • 64KB of On-chip RAM with SECDED ECC in Device/Power Manager Subsystem
    • 1.25MB of L2 SRAM with SECDED ECC in C7x Deep Learning Accelerator
  • DDR Subsystem (DDRSS)
    • Supports LPDDR4
    • 32-bit data bus with inline ECC
    • Supports speeds up to 3733MT/s
    • Max addressable range of 8GBytes

Functional Safety:

  • Functional Safety-Compliant targeted [Industrial]
    • Developed for functional safety applications
    • Documentation will be available to aid IEC 61508 functional safety system design
    • Systematic capability up to SIL 3 targeted
    • Hardware Integrity up to SIL 2 targeted
    • Safety-related certification
      • IEC 61508 by TÜV SÜD planned
  • Functional Safety-Compliant targeted [Automotive]
    • Developed for functional safety applications
    • Documentation will be available to aid ISO 26262 functional safety system design
    • Systematic capability up to ASIL D targeted
    • Hardware integrity up to ASIL B targeted
    • Safety-related certification
      • ISO 26262 by TÜV SÜD planned
  • AEC - Q100 qualified [Automotive]

Security:

  • Secure boot supported
    • Hardware-enforced Root-of-Trust (RoT)
    • Support to switch RoT via backup key
    • Support for takeover protection, IP protection, and anti-roll back protection
  • Trusted Execution Environment (TEE) supported
    • Arm TrustZone based TEE
    • Extensive firewall support for isolation
    • Secure watchdog/timer/IPC
    • Secure storage support
    • Replay Protected Memory Block (RPMB) support
  • Dedicated Security Controller with user programmable HSM core and dedicated security DMA & IPC subsystem for isolated processing
  • Cryptographic acceleration supported
    • Session-aware cryptographic engine with ability to auto-switch key-material based on incoming data stream
      • Supports cryptographic cores
    • AES – 128-/192-/256-Bit key sizes
    • SHA2 – 224-/256-/384-/512-Bit key sizes
    • DRBG with true random number generator
    • PKA (Public Key Accelerator) to Assist in RSA/ECC processing for secure boot
  • Debugging security
    • Secure software controlled debug access
    • Security aware debugging

High-Speed Interfaces:

  • Integrated Ethernet switch supporting (total 2 external ports)
    • RMII(10/100) or RGMII (10/100/1000)
    • IEEE1588 (Annex D, Annex E, Annex F with 802.1AS PTP)
    • Clause 45 MDIO PHY management
    • Packet Classifier based on ALE engine with 512 classifiers
    • Priority based flow control
    • Time Sensitive Networking (TSN) support
    • Four CPU H/W interrupt Pacing
    • IP/UDP/TCP checksum offload in hardware
  • Two USB2.0 Ports
    • Port configurable as USB host, USB peripheral, or USB Dual-Role Device (DRD mode)
    • Integrated USB VBUS detection

General Connectivity:

  • 9x Universal Asynchronous Receiver-Transmitters (UART)
  • 5x Serial Peripheral Interface (SPI) controllers
  • 6x Inter-Integrated Circuit (I2C) ports
  • 3x Multichannel Audio Serial Ports (McASP)
    • Transmit and Receive Clocks up to 50MHz
    • Up to 4/6/16 Serial Data Pins across 3x McASP with Independent TX and RX Clocks
    • Supports Time Division Multiplexing (TDM), Inter-IC Sound (I2S), and Similar Formats
    • Supports Digital Audio Interface Transmission (SPDIF, IEC60958-1, and AES-3 Formats)
    • FIFO Buffers for Transmit and Receive (256 Bytes)
    • Support for audio reference output clock
  • 3x enhanced PWM modules (ePWM)
  • 3x enhanced Quadrature Encoder Pulse modules (eQEP)
  • 3x enhanced Capture modules (eCAP)
  • General-Purpose I/O (GPIO), All LVCMOS I/O can be configured as GPIO
  • 3x Controller Area Network (CAN) modules with CAN-FD support
    • Conforms w/ CAN Protocol 2.0 A, B and ISO 11898-1
    • Full CAN FD support (up to 64 data bytes)
    • Parity/ECC check for Message RAM
    • Speed up to 8Mbps

Media and Data Storage:

  • 3x Multi-Media Card/Secure Digital (MMC/SD/SDIO) interface
    • 1x 8-bit eMMC interface up to HS200 speed
    • 2x 4-bit SD/SDIO interface up to UHS-I
    • Compliant with eMMC 5.1, SD 3.0, and SDIO Version 3.0
  • 1× General-Purpose Memory Controller (GPMC) up to 133MHz
    • Flexible 8- and 16-bit Asynchronous Memory Interface with up to four Chip (22-bit address) Selects (NAND, NOR, Muxed-NOR, and SRAM)
    • Uses BCH code to support 4-, 8-, or 16-bit ECC
    • Uses Hamming code to support 1-bit ECC
    • Error Locator Module (ELM)
      • Used with the GPMC to locate addresses of data errors from syndrome polynomials generated using a BCH algorithm
      • Supports 4-, 8-, and 16-bit per 512-Byte block error location based on BCH algorithms
  • OSPI/QSPI with DDR / SDR support
    • Support for Serial NAND and Serial NOR Flash devices
    • 4GBytes memory address support
    • XIP mode with optional on-the-fly encryption

Power Management:

  • Low-power modes supported by Device/Power Manager
    • Partial IO support for CAN/GPIO/UART wakeup
    • DeepSleep : I/O + DDR (suspend to RAM)
    • DeepSleep
    • MCU Only
    • Standby
    • Dynamic frequency scaling for Cortex-A53

Boot Options:

  • UART
  • I2C EEPROM
  • OSPI/QSPI Flash
  • GPMC NOR/NAND Flash
  • Serial NAND Flash
  • SD Card
  • eMMC
  • USB (host) boot from Mass Storage device
  • USB (device) boot from external host (DFU mode)
  • Ethernet

Technology / Package:

  • 16-nm FinFET technology
  • 18mm x 18mm, 0.8mm pitch full-array, 484-pin FCBGA (AMB)
  • 18mm x 18mm, 0.8mm pitch full-array, 484-pin FCCSP (ANF)

AM62Ax is an extension of the Sitara™ automotive-grade family of heterogeneous Arm® processors with embedded Deep Learning (DL), Video and Vision Processing acceleration, display interface and extensive automotive peripheral and networking options. AM62Ax is built for a set of cost-sensitive automotive applications including driver and in-cabin monitoring systems, next generation of eMirror system, as well as a broad set of industrial applications in Factory Automation, Building Automation, Robotics, and other markets. The cost optimized AM62Ax provides high-performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in stand-alone Electronic Control Units (ECUs).

AM62Ax contains up to four Arm® Cortex®-A53 cores with 64-bit architecture, a Vision Processing Accelerator (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Deep Learning (DL) and video accelerators, a Cortex®-R5F MCU Channel core and a Cortex®-R5F Device Management core. The Cortex-A53s provide the powerful computing elements necessary for Linux applications as well as the implementation of traditional vision computing based-algorithms such as driver monitoring. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite including RGB-InfraRed (RGB-IR), support for higher bit depth, and features targeting analytics applications. Key cores include the next generation C7000™ DSP from Texas Instruments (“C7x”) with scalar and vector cores, dedicated “MMA” deep learning accelerator enabling performance up to 2 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C.

The 3-port Gigabit Ethernet switch has one internal port and two external ports with TSN support and can be used to enable industrial networking options. In addition, an extensive peripherals set is included in AM62Ax to enable system level connectivity such as USB, MMC/SD, Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. AM62Ax supports secure boot for IP protection with the built-in HSM (Hardware Security Module) and also employs advanced power management support for portable and power-sensitive applications.

AM62Ax is an extension of the Sitara™ automotive-grade family of heterogeneous Arm® processors with embedded Deep Learning (DL), Video and Vision Processing acceleration, display interface and extensive automotive peripheral and networking options. AM62Ax is built for a set of cost-sensitive automotive applications including driver and in-cabin monitoring systems, next generation of eMirror system, as well as a broad set of industrial applications in Factory Automation, Building Automation, Robotics, and other markets. The cost optimized AM62Ax provides high-performance compute for both traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor modalities in stand-alone Electronic Control Units (ECUs).

AM62Ax contains up to four Arm® Cortex®-A53 cores with 64-bit architecture, a Vision Processing Accelerator (VPAC) with Image Signal Processor (ISP) and multiple vision assist accelerators, Deep Learning (DL) and video accelerators, a Cortex®-R5F MCU Channel core and a Cortex®-R5F Device Management core. The Cortex-A53s provide the powerful computing elements necessary for Linux applications as well as the implementation of traditional vision computing based-algorithms such as driver monitoring. Building on the existing world-class ISP, TI’s 7th generation ISP includes flexibility to process a broader sensor suite including RGB-InfraRed (RGB-IR), support for higher bit depth, and features targeting analytics applications. Key cores include the next generation C7000™ DSP from Texas Instruments (“C7x”) with scalar and vector cores, dedicated “MMA” deep learning accelerator enabling performance up to 2 TOPS within the lowest power envelope in the industry when operating at the typical automotive worst case junction temperature of 125°C.

The 3-port Gigabit Ethernet switch has one internal port and two external ports with TSN support and can be used to enable industrial networking options. In addition, an extensive peripherals set is included in AM62Ax to enable system level connectivity such as USB, MMC/SD, Camera interface, OSPI, CAN-FD and GPMC for parallel host interface to an external ASIC/FPGA. AM62Ax supports secure boot for IP protection with the built-in HSM (Hardware Security Module) and also employs advanced power management support for portable and power-sensitive applications.

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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet AM62Ax Sitara™ Processors datasheet (Rev. D) PDF | HTML 20 Jun 2025
* Errata AM62Ax Sitara™ Processors Silicon Errata, Silicon Revision 1.0 (Rev. C) PDF | HTML 10 Oct 2025
* User guide AM62Ax Sitara Processors Technical Reference Manual (Rev. C) 08 Dec 2025
Application note Enabling Matter on Sitara MPU (Rev. A) PDF | HTML 24 Nov 2025
Application note AM62x Audio Design Guide PDF | HTML 20 Nov 2025
User guide Hardware Design Considerations for Custom Board Design using AM62A3, AM62A7-Q1, AM62A1-Q1, AM62D-Q1 Processor (Rev. D) PDF | HTML 24 Oct 2025
User guide AM62A3, AM62A7-Q1, AM62A1-Q1, AM62D-Q1 Processor Family Schematic, Design Guidelines and Review Checklist (Rev. C) PDF | HTML 17 Sep 2025
User guide AM62x, AM62Ax, AM62D-Q1 and AM62Px Processor Family Schematic, Design Guidelines and Review Checklist (Rev. I) PDF | HTML 17 Sep 2025
Application note AM62x, AM62Ax, AM62Px, AM62Lx Spread-Spectrum Clocking PDF | HTML 08 Sep 2025
Application note Custom Board Design and Simulation Guidelines for Processor High Speed Parallel Interfaces (Rev. A) PDF | HTML 05 Sep 2025
Functional safety information AM6x, AM24x Software Diagnostics Library TÜV SÜD Functional Safety Certificate for 9.2.0 SDK (Rev. A) 17 Jul 2025
Application note AM62Ax Power-Estimation Tool (PET)-- (Rev. B) PDF | HTML 07 Mar 2025
White paper Securing Arm-Based Application Processors (Rev. F) PDF | HTML 26 Feb 2025
User guide AM62Ax/AM62Dx Escape Routing for PCB Design (Rev. A) PDF | HTML 14 Jan 2025
Application note AM62Ax, AM62Px LPDDR4 Board Design and Layout Guidelines (Rev. B) PDF | HTML 17 Dec 2024
Application note Basic Ethernet Interface Debug With Linux PDF | HTML 11 Oct 2024
Application note Minimal Platform Development on AM62x Devices (Rev. A) PDF | HTML 24 Sep 2024
Application note AM6xA ISP Tuning Guide (Rev. A) PDF | HTML 08 May 2024
Application note Developing Multiple-Camera Applications on AM6x (Rev. A) PDF | HTML 14 Feb 2024
Technical article What’s the best type of computer vision for AI applications? PDF | HTML 05 Jan 2024
Application note Multimedia Applications on AM62A PDF | HTML 29 Nov 2023
Application note Using TSN Ethernet Features to Improve Timing in Industrial Ethernet Controllers PDF | HTML 15 Nov 2023
Application brief Keyword Spotting Using AI at the Edge With Sitara Processors PDF | HTML 28 Sep 2023
White paper Time Sensitive Networking for Industrial Automation (Rev. C) 31 Jul 2023
Application note Vision AI-Based Defect Detection on AM62A Using TI Edge AI Studio PDF | HTML 28 Jul 2023
User guide TPS65931211-Q1 PMIC User Guide for AM62A PDF | HTML 27 Jul 2023
White paper Driver and Occupancy Monitoring Systems on AM62A PDF | HTML 12 Jul 2023
Application brief AM62A Soc Improves Barcode Readers with Hardware Accelerated Vision Processing 29 Jun 2023
White paper Camera Mirror Systems on AM62A PDF | HTML 09 Jun 2023
Application note AM62A Edge AI Retail Scanner Demo: Analysis for SoC Selection and Power Usage PDF | HTML 30 May 2023
White paper Easing the Pain of Safety Certified System Development PDF | HTML 24 May 2023
Application note Building an Edge AI Application for Automated Retail Scanner on AM6xA MPUs PDF | HTML 17 May 2023
Application note AM62Ax Maximum Current Ratings PDF | HTML 18 Apr 2023
White paper Edge AI Smart Cameras Using Energy-Efficient AM62A Processor PDF | HTML 02 Mar 2023
Application note Sitara™AM62A Benchmarks PDF | HTML 01 Mar 2023
Application note High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 24 Feb 2023
Application note McASP Design Guide - Tips, Tricks, and Practical Examples 10 Jan 2019
White paper Secure Boot on embedded Sitara™ processors (Rev. A) 13 Oct 2018

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

Evaluation board

SK-AM62A-LP — AM62A starter kit for low-power Sitara™ processors

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Lauterbach‘s TRACE32® tools are a suite of leading-edge hardware and software components that enables developers to analyze, optimize and certify all kinds of Arm®-based microcontrollers and processors. The globally renowned debug and trace solutions for embedded systems and SoCs are the perfect (...)

Software development kit (SDK)

MCU-PLUS-SDK-AM62A MCU+ SDK for AM62A – RTOS, No-RTOS

The AM62A vision processor Linux® and TI MCU plus software development kits (SDKs) are unified software platforms for our embedded processors with deep learning capabilities with edge AI. They provide easy setup and fast out-of-the-box access to benchmarks and demonstrations. AM62A is a high (...)

Supported products & hardware

Supported products & hardware

Browse Download options
Software development kit (SDK)

PROCESSOR-SDK-QNX-AM62AX QNX software development kit for AM62A Sitara™ processors

The AM62A vision processor Linux® and TI MCU plus software development kits (SDKs) are unified software platforms for our embedded processors with deep learning capabilities with edge AI. They provide easy setup and fast out-of-the-box access to benchmarks and demonstrations. AM62A is a high (...)

Supported products & hardware

Supported products & hardware

Firmware

USIT-3P-SECIC-HSM — Uni-Sentry SecIC-HSM Firmware

The SecIC-HSM is designed to meet the cybersecurity requirements needed for MCU/SoC chips. The HSM firmware can be applied in fields such as automobiles, new energy, photovoltaics, robotics, healthcare, and aviation. The provided cybersecurity functions available include secure boot, secure (...)
Firmware

USIT-3P-SECIC-PQC — Uni-Sentry SecIC-PQC Algorithms Firmware

Uni-Sentry's security solutions adopt PQC algorithms capable of resisting decryption threats posed by quantum computers to traditional cryptographic algorithms. The PQC firmware is co-optimized with Hardware Security Module (HSM), leveraging hardware acceleration and security enhancement to improve (...)
Getting started

TI-DEVELOPER-ZONE Start embedded development on your desktop or in the cloud

From evaluation to deployment the TI Developer Zone provides a comprehensive range of software, tools and training to ensure that you have everything you need for each stage of the development process.
Supported products & hardware

Supported products & hardware

IDE, configuration, compiler or debugger

CCSTUDIO CCStudio™ IDE

CCStudio™ IDE is part of TI's extensive CCStudio™ development tool ecosystem. It is an integrated development environment (IDE) for TI's microcontrollers, processors, wireless connectivity devices and radar sensors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize (...)

Supported products & hardware

Supported products & hardware

Launch Download options
IDE, configuration, compiler or debugger

CLOCKTREE-AM62AX Clock tree configuration for AM62Ax


The Clock Tree Tool (CTT) for ARM Processors & Digital Signal Processors is an interactive configuration software tool that provides information about device clock tree architecture. This tool allows visualization of the device clock tree. It can also be used to determine the exact register (...)

Supported products & hardware

Supported products & hardware

IDE, configuration, compiler or debugger

DDR-CONFIG-AM62A DDR Configuration Tool

This SysConfig based tool simplifies the process of configuring the DDR Subsystem Controller and PHY to interface to SDRAM devices. Based on the memory device, board design, and topology the tool outputs files to initialize and train the selected memory.
Supported products & hardware

Supported products & hardware

IDE, configuration, compiler or debugger

EDGE-AI-STUDIO Edge AI Studio

Edge AI Studio is part of the CCStudio™ development tool ecosystem.  Edge AI Studio is a collection of graphical and command line tools designed to accelerate edge AI development on TI processors, microcontrollers, connectivity devices and radar sensors.  It supports both AI-accelerated (...)

Supported products & hardware

Supported products & hardware

IDE, configuration, compiler or debugger

K3-RESOURCE-CONFIGURATION Resource partitioning tool for multi core SOCs

Also known as the k3-respart-tool, the Resource Configuration tool allows for configuration of various system level parameters and generate the necessary data to be fed into software components
Supported products & hardware

Supported products & hardware

IDE, configuration, compiler or debugger

SYSCONFIG Standalone desktop version of SysConfig

SysConfig is a configuration tool designed to simplify hardware and software configuration challenges to accelerate software development.

SysConfig is available as part of the Code Composer Studio™ integrated development environment as well as a standalone application. Additionally SysConfig (...)

Supported products & hardware

Supported products & hardware

Launch Download options
Online training

AM62A-ACADEMY AM62Ax Academy

AM62Ax Academy is designed to simplify and accelerate development on AM62Ax processors.
Supported products & hardware

Supported products & hardware

Operating system (OS)

WHIS-3P-SAFERTOS — WITTENSTEIN SAFERTOS Pre-certified safety RTOS

SAFERTOS® is a unique real time operating system designed for embedded processors. It is precertified to IEC 61508 SIL3 and ISO 26262 ASILD standards by TÜV SÜD. SAFERTOS® was crafted specifically for safety by WHIS' team of experts and is used globally in safety critical applications. WHIS and (...)
Package Pins CAD symbols, footprints & 3D models
FCCSP (ANF) 484 Ultra Librarian

Ordering & quality

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  • Ongoing reliability monitoring
Information included:
  • Fab location
  • Assembly location

Recommended products may have parameters, evaluation modules or reference designs related to this TI product.

Support & training

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