CODELOADER
CodeLoader 器件寄存器编程
CODELOADER
概述
The CodeLoader 4 software is used to program the LMX PLLs and LMK timing devices through either the USB or line print terminal (LPT) port of a computer. This software also provides information on how to program the device by showing the bits that are actually sent.
Which software do I use?
Product | Loop filter & device configuration + simulation | Device register programming |
LMX24xx PLL family | EasyPLL | CodeLoader* |
LMX25xx PLL+VCO family | ||
LMK jitter cleaners and distributors |
*For new designs, use the Clocks and Synthesizers (TICS) Pro Software tool.
下载
软件编程工具
The design resource accessed as www.ti.com.cn/lit/zip/snac014 or www.ti.com.cn/lit/xx/snac014e/snac014e.zip has been migrated to a new user experience at www.ti.com.cn/tool/cn/download/SNAC014. Please update any bookmarks accordingly.
您可能需要的其他资源
支持软件
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
支持的产品和硬件
产品
射频 PLL 与合成器
振荡器
时钟发生器
时钟抖动清除器
时钟缓冲器
时钟网络同步器
硬件开发
评估板
TICSPRO-SW — TICS Pro GUI and Live Programming Tool for Clocking Devices
TICS Pro 1.7.7.10 installer binary for Windows operating system
产品
射频 PLL 与合成器
振荡器
时钟发生器
时钟抖动清除器
时钟缓冲器
时钟网络同步器
硬件开发
评估板
文档
TICS Pro 1.7.7.10 Software Manifest
TICS Pro 1.7.7.10 Release Notes
发布信息
Bug Fixes
- LMK05028 - bugfixes to frequency updates and DPLL coefficient script
Known Issues
- LMK5B and LMK5C family - In some cases, "Assign Selected VCO Settings to Device" and "Apply Output Clock Settings to Device" may need to be pressed twice for certain cascaded configurations to display correctly
- LMK5C33216 - When cascading from VCO3 to DPLL input, the divide value must manually be entered into DPLLx_REF5_RDIV as ( VCO3 output frequency / DPLLx TDC frequency )
- LMK05318 - In some cases, it is necessary to press "Calculate Frequency Plan" twice for correct VCO2 frequency. This issue is resolved in LMK05318B GUI.
- Burst mode page looping requires long delays to halt, and halting may crash the GUI. If possible, do not loop in burst mode.
- User Controls page can sometimes become desynchronized from Raw Registers and other pages. Refer to Raw Registers or other pages for correct values. Saving/Loading and Import/Export of register data is unaffected, and register data will still be written to and read from connected devices correctly.
设计工具
PLLATINUMSIM-SW — PLLatinum Sim Tool
支持的产品和硬件
产品
IQ 解调器
射频 PLL 与合成器
时钟发生器
时钟抖动清除器
时钟缓冲器
时钟网络同步器
硬件开发
评估板
PLLATINUMSIM-SW — PLLatinum Sim Tool
产品
IQ 解调器
射频 PLL 与合成器
时钟发生器
时钟抖动清除器
时钟缓冲器
时钟网络同步器
硬件开发
评估板
发布信息
Bug fixes
新增功能
- Fixed Kvco calculation bug introduced in 1.6.6
- Added warning for loop bandwidth being restricted due to min high order capacitance.
技术文档
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