TLC4545
- 200-KSPS Sampling Rate
- Built-In Conversion Clock
- INL: ±2.5 LSB Max,
DNL: 2 to –1 LSB Max - SINAD = 84.5 dB, SFDR = 95 dB,
THD = 94 dB at 15 kHz fin, 200 KSPS - SPI/DSP-Compatible Serial Interfaces With SCLK Input up to 15 MHz
- Single 5-V Supply
- Rail-to-Rail Analog Input With 500 kHz BW
- Two Input Options Available:
- TLC4541 – Single Channel Input
- TLC4545 – Single Channel, Pseudo-differential Input
- (TLC4541) Optimized DSP Interface – Requires FS Input Only
- Low Power With Auto-Power Down
- Operating Current: 3.5 mA
- Auto-Power Down Current: 5 uA
- Pin Compatible 12/14/16-Bit Family in 8-Pin SOIC and MSOP Packages
- APPLICATIONS
- ATE System
- Industrial Process Control
- Measurement
- Motor Control
The TLC4541 and TLC4545 are a family of high performance, 16-bit, low power, miniature CMOS analog-to-digital converters (ADCs). These devices operate from a single 5-V supply. Devices are available with single, dual, or single pseudo-differential inputs. All of these devices have a chip select (CS)\, serial clock (SCLK), and serial data output (SDO) that provides a direct 3-wire interface to the serial port of most popular host microprocessors (SPI interface). When interfaced with a DSP, a frame sync signal (FS) is used to indicate the start of a serial data frame on either pin 1 (CS)\ or pin 7 (FS) for the TLC4541. The TLC4545 ADC connects to the DSP via pin 1 only (CS)\.
The TLC4541 and TLC4545 are designed to operate with low power consumption. The power saving feature is further enhanced with an auto-power down mode. This product family features a high-speed serial link to modern host processors with an external SCLK up to 15 MHz. Both families use a built-in oscillator as the conversion clock, providing a 2.94 us maximum conversion time.
Technical documentation
Type | Title | Date | ||
---|---|---|---|---|
* | Data sheet | 5-V, Low Power- 16-/14-Bit 100-200 KSPS Serial ADC with Auto-Power Down datasheet | 10 Jul 2000 | |
White paper | Voltage-reference impact on total harmonic distortion | 01 Aug 2016 | ||
E-book | Best of Baker's Best: Precision Data Converters -- SAR ADCs | 21 May 2015 | ||
Application note | Determining Minimum Acquisition Times for SAR ADCs, part 2 | 17 Mar 2011 |
Design & development
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5-6KINTERFACE — 5-6K Interface Evaluation Module
The interface board consists of two signal conditioning sites, two serial EVM sites, and a parallel EVM site. Regardless of the interface type, all EVMs compatible with the 5-6K Interface Board have a standard analog interface and standard power connector. Three position screw terminals J1 and J2 (...)
ANALOG-ENGINEER-CALC — Analog engineer's calculator
PSPICE-FOR-TI — PSpice® for TI design and simulation tool
TINA-TI — SPICE-based analog simulation program
Package | Pins | CAD symbols, footprints & 3D models |
---|---|---|
SOIC (D) | 8 | Ultra Librarian |
VSSOP (DGK) | 8 | Ultra Librarian |
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