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AM3894

アクティブ

Sitara プロセッサ：Arm Cortex-A8、3D グラフィックス、HDMI

ご注文はこちら
データシート
ユーザー ガイド
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AM3894

アクティブ
データシート ご注文はこちら

製品詳細

CPU 1 Arm Cortex-A8 Frequency (MHz) 1200 Graphics acceleration 1 3D Display type 1 HDMI, 2 LCD PCIe 1 PCIe Gen 2 Operating system Linux, RTOS Rating Catalog Operating temperature range (°C) -40 to 105
CPU 1 Arm Cortex-A8 Frequency (MHz) 1200 Graphics acceleration 1 3D Display type 1 HDMI, 2 LCD PCIe 1 PCIe Gen 2 Operating system Linux, RTOS Rating Catalog Operating temperature range (°C) -40 to 105
FCBGA (CYG) 1031 625 mm² 25 x 25
  • High-Performance Sitara ARM Microprocessors (MPUs)
    • ARMCortex-A8 RISC Processor
      • Up to 1.20 GHz
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • In-Order, Dual-Issue, Superscalar Processor Core
      • NEON Multimedia Architecture
    • Supports Integer and Floating Point (VFPv3-IEEE754 Compliant)
      • Jazelle RCT Execution Environment
  • ARM Cortex-A8 Memory Architecture
    • 32-KB Instruction and Data Caches
    • 256-KB L2 Cache
    • 64-KB RAM, 48-KB of Boot ROM
  • 512KB of On-Chip Memory Controller (OCMC) RAM
  • SGX530 3D Graphics Engine (Available Only on the AM3894 Device)
    • Delivers up to 30 MTriangles per Second
    • Universal Scalable Shader Engine
    • Direct3D Mobile, OpenGL ES 1.1 and 2.0, OpenVG 1.1, OpenMax API Support
    • Advanced Geometry DMA Driven Operation
    • Programmable HQ Image Anti-Aliasing
  • Endianness
    • ARM Instructions and Data – Little Endian
  • HD Video Processing Subsystem (HDVPSS)
    • Two 165-MHz HD Video Capture Channels
      • One 16-Bit or 24-Bit and One 16-Bit Channel
      • Each Channel Splittable Into Dual 8-Bit Capture Channels
    • Two 165-MHz HD Video Display Channels
      • One 16-Bit, 24-Bit, 30-Bit Channel and One 16-Bit Channel
    • Simultaneous SD and HD Analog Output
    • Digital HDMI 1.3 Transmitter with PHY with HDCP up to 165-MHz Pixel Clock
    • Three Graphics Layers
  • Dual 32-Bit DDR2 and DDR3 SDRAM Interfaces
    • Supports up to DDR2-800 and DDR3-1600
    • Up to Eight x8 Devices Total
    • 2GB of Total Address Space
    • Dynamic Memory Manager (DMM)
      • Programmable Multi-Zone Memory Mapping and Interleaving
      • Enables Efficient 2D Block Accesses
      • Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
      • Optimizes Interlaced Accesses
  • One PCI Express (PCIe) 2.0 Port with Integrated PHY
    • Single Port with 1 or 2 Lanes at 5.0 GT per Second
    • Configurable as Root Complex or Endpoint
  • Serial ATA (SATA) 3.0 Gbps Controller with Integrated PHYs
    • Direct Interface for Two Hard Disk Drives
    • Hardware-Assisted Native Command Queuing (NCQ) from up to 32 Entries
    • Supports Port Multiplier and Command-Based Switching
  • Two 10 Mbps, 100 Mbps, and 1000 Mbps Ethernet MACs (EMAC)
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • MII and GMII Media Independent Interfaces
    • Management Data I/O (MDIO) Module
  • Dual USB 2.0 Ports with Integrated PHYs
    • USB 2.0 High-Speed and Full-Speed Client
    • USB 2.0 High-Speed, Full-Speed, and Low-Speed Host
    • Supports Endpoints 0-15
  • General-Purpose Memory Controller (GPMC)
    • 8-Bit and 16-Bit Multiplexed Address and Data Bus
    • Up to 6 Chip Selects with up to 256-MB Address Space per Chip Select Pin
    • Glueless Interface to NOR Flash, NAND Flash (with BCH and Hamming Error Code Detection), SRAM and Pseudo-SRAM
    • Error Locator Module (ELM) Outside of GPMC to Provide up to 16-Bit and 512-Byte Hardware ECC for NAND
    • Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs
  • Enhanced Direct-Memory-Access (EDMA) Controller
    • Four Transfer Controllers
    • 64 Independent DMA Channels and 8 Quick DMA (QDMA) Channels
  • Seven 32-Bit General-Purpose Timers
  • One System Watchdog Timer
  • Three Configurable UART, IrDA, and CIR Modules
    • UART0 with Modem Control Signals
    • Supports up to 3.6864 Mbps UART
    • SIR, MIR, FIR (4.0 MBAUD), and CIR
  • One 40-MHz Serial Peripheral Interface (SPI) with Four Chip Selects
  • SD and SDIO Serial Interface (1-Bit and 4-Bit)
  • Dual Inter-Integrated Circuit (I2C bus) Ports
  • Three Multichannel Audio Serial Ports (McASPs)
    • One Six-Serializer Transmit and Receive Port
    • Two Dual-Serializer Transmit and Receive Ports
    • DIT-Capable For SDIF and PDIF (All Ports)
  • Multichannel Buffered Serial Port (McBSP)
    • Transmit and Receive Clocks up to 48 MHz
    • Two Clock Zones and Two Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
  • Real-Time Clock (RTC)
    • One-Time or Periodic Interrupt Generation
  • Up to 64 General-Purpose I/O (GPIO) Pins
  • On-Chip ARM ROM Bootloader (RBL)
  • Power, Reset, and Clock Management
    • SmartReflex Technology (Level 2)
    • Seven Independent Core Power Domains
    • Clock Enable and Disable Control For Subsystems and Peripherals
  • IEEE 1149.1 (JTAG) and IEEE 1149.7 (cJTAG) Compatible
  • Via Channel Technology Enables use of
    0.8-mm Design Rules
  • 40-nm CMOS Technology
  • 3.3-V Single-Ended LVCMOS I/Os (Except for DDR3 at 1.5 V, DDR2 at 1.8 V, and DEV_CLKIN at 1.8 V)
  • High-Performance Sitara ARM Microprocessors (MPUs)
    • ARMCortex-A8 RISC Processor
      • Up to 1.20 GHz
  • ARM Cortex-A8 Core
    • ARMv7 Architecture
      • In-Order, Dual-Issue, Superscalar Processor Core
      • NEON Multimedia Architecture
    • Supports Integer and Floating Point (VFPv3-IEEE754 Compliant)
      • Jazelle RCT Execution Environment
  • ARM Cortex-A8 Memory Architecture
    • 32-KB Instruction and Data Caches
    • 256-KB L2 Cache
    • 64-KB RAM, 48-KB of Boot ROM
  • 512KB of On-Chip Memory Controller (OCMC) RAM
  • SGX530 3D Graphics Engine (Available Only on the AM3894 Device)
    • Delivers up to 30 MTriangles per Second
    • Universal Scalable Shader Engine
    • Direct3D Mobile, OpenGL ES 1.1 and 2.0, OpenVG 1.1, OpenMax API Support
    • Advanced Geometry DMA Driven Operation
    • Programmable HQ Image Anti-Aliasing
  • Endianness
    • ARM Instructions and Data – Little Endian
  • HD Video Processing Subsystem (HDVPSS)
    • Two 165-MHz HD Video Capture Channels
      • One 16-Bit or 24-Bit and One 16-Bit Channel
      • Each Channel Splittable Into Dual 8-Bit Capture Channels
    • Two 165-MHz HD Video Display Channels
      • One 16-Bit, 24-Bit, 30-Bit Channel and One 16-Bit Channel
    • Simultaneous SD and HD Analog Output
    • Digital HDMI 1.3 Transmitter with PHY with HDCP up to 165-MHz Pixel Clock
    • Three Graphics Layers
  • Dual 32-Bit DDR2 and DDR3 SDRAM Interfaces
    • Supports up to DDR2-800 and DDR3-1600
    • Up to Eight x8 Devices Total
    • 2GB of Total Address Space
    • Dynamic Memory Manager (DMM)
      • Programmable Multi-Zone Memory Mapping and Interleaving
      • Enables Efficient 2D Block Accesses
      • Supports Tiled Objects in 0°, 90°, 180°, or 270° Orientation and Mirroring
      • Optimizes Interlaced Accesses
  • One PCI Express (PCIe) 2.0 Port with Integrated PHY
    • Single Port with 1 or 2 Lanes at 5.0 GT per Second
    • Configurable as Root Complex or Endpoint
  • Serial ATA (SATA) 3.0 Gbps Controller with Integrated PHYs
    • Direct Interface for Two Hard Disk Drives
    • Hardware-Assisted Native Command Queuing (NCQ) from up to 32 Entries
    • Supports Port Multiplier and Command-Based Switching
  • Two 10 Mbps, 100 Mbps, and 1000 Mbps Ethernet MACs (EMAC)
    • IEEE 802.3 Compliant (3.3-V I/O Only)
    • MII and GMII Media Independent Interfaces
    • Management Data I/O (MDIO) Module
  • Dual USB 2.0 Ports with Integrated PHYs
    • USB 2.0 High-Speed and Full-Speed Client
    • USB 2.0 High-Speed, Full-Speed, and Low-Speed Host
    • Supports Endpoints 0-15
  • General-Purpose Memory Controller (GPMC)
    • 8-Bit and 16-Bit Multiplexed Address and Data Bus
    • Up to 6 Chip Selects with up to 256-MB Address Space per Chip Select Pin
    • Glueless Interface to NOR Flash, NAND Flash (with BCH and Hamming Error Code Detection), SRAM and Pseudo-SRAM
    • Error Locator Module (ELM) Outside of GPMC to Provide up to 16-Bit and 512-Byte Hardware ECC for NAND
    • Flexible Asynchronous Protocol Control for Interface to FPGA, CPLD, ASICs
  • Enhanced Direct-Memory-Access (EDMA) Controller
    • Four Transfer Controllers
    • 64 Independent DMA Channels and 8 Quick DMA (QDMA) Channels
  • Seven 32-Bit General-Purpose Timers
  • One System Watchdog Timer
  • Three Configurable UART, IrDA, and CIR Modules
    • UART0 with Modem Control Signals
    • Supports up to 3.6864 Mbps UART
    • SIR, MIR, FIR (4.0 MBAUD), and CIR
  • One 40-MHz Serial Peripheral Interface (SPI) with Four Chip Selects
  • SD and SDIO Serial Interface (1-Bit and 4-Bit)
  • Dual Inter-Integrated Circuit (I2C bus) Ports
  • Three Multichannel Audio Serial Ports (McASPs)
    • One Six-Serializer Transmit and Receive Port
    • Two Dual-Serializer Transmit and Receive Ports
    • DIT-Capable For SDIF and PDIF (All Ports)
  • Multichannel Buffered Serial Port (McBSP)
    • Transmit and Receive Clocks up to 48 MHz
    • Two Clock Zones and Two Serial Data Pins
    • Supports TDM, I2S, and Similar Formats
  • Real-Time Clock (RTC)
    • One-Time or Periodic Interrupt Generation
  • Up to 64 General-Purpose I/O (GPIO) Pins
  • On-Chip ARM ROM Bootloader (RBL)
  • Power, Reset, and Clock Management
    • SmartReflex Technology (Level 2)
    • Seven Independent Core Power Domains
    • Clock Enable and Disable Control For Subsystems and Peripherals
  • IEEE 1149.1 (JTAG) and IEEE 1149.7 (cJTAG) Compatible
  • Via Channel Technology Enables use of
    0.8-mm Design Rules
  • 40-nm CMOS Technology
  • 3.3-V Single-Ended LVCMOS I/Os (Except for DDR3 at 1.5 V, DDR2 at 1.8 V, and DEV_CLKIN at 1.8 V)

The AM389x Sitara ARM processors are a highly integrated, programmable platform that leverages TI's Sitara technology to meet the processing needs of the following applications: single-board computing, network and communications processing, industrial automation, human machine interface, and interactive point-of-service kiosks.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device combines high-performance ARM processing with a highly integrated peripheral set.

The ARM Cortex-A8 32-bit RISC processor with NEON floating-point extension includes: 32KB of instruction cache; 32KB of data cache; 256KB of L2 cache; and 64KB of RAM.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD video processing subsystem (HDVPSS), which provides output of simultaneous HD and SD analog video and dual HD video inputs; up to two Gigabit Ethernet MACs (10 Mbps,100, Mbps, 1000 Mbps) with GMII and MDIO interface; two USB ports with integrated 2.0 PHY; PCIe port x2 lanes GEN2 compliant interface, which allows the device to act as a PCIe root complex or device endpoint; one 6-channel McASP audio serial port (with DIT mode); two dual-channel McASP audio serial ports (with DIT mode); one McBSP multichannel buffered serial port; three UARTs with IrDA and CIR support; SPI serial interface; SD and SDIO serial interface; two I2C master and slave interfaces; up to 64 GPIO pins; seven 32-bit timers; system watchdog timer; dual DDR2 and DDR3 SDRAM interface; flexible 8-bit and 16-bit asynchronous memory interface; and up to two SATA interfaces for external storage on two disk drives or more with the use of a port multiplier.

The device also includes an SGX530 3D graphics engine (available only on the AM3894 device) to off-load many video and imaging processing tasks from the core. Additionally, the device has a complete set of development tools for the ARM, including C compilers and a Microsoft Windows debugger interface for visibility into source code execution.

The device package has been specially engineered with Via Channel technology. This technology allows use of 0.8-mm pitch PCB feature sizes in this 0.65-mm pitch package, and substantially reduces PCB costs. Via Channel technology also allows PCB routing in only two signal layers due to the increased layer efficiency of the Via Channel BGA technology.

The AM389x Sitara ARM processors are a highly integrated, programmable platform that leverages TI's Sitara technology to meet the processing needs of the following applications: single-board computing, network and communications processing, industrial automation, human machine interface, and interactive point-of-service kiosks.

The device enables original-equipment manufacturers (OEMs) and original-design manufacturers (ODMs) to quickly bring to market devices featuring robust operating systems support, rich user interfaces, and high processing performance through the maximum flexibility of a fully integrated mixed processor solution. The device combines high-performance ARM processing with a highly integrated peripheral set.

The ARM Cortex-A8 32-bit RISC processor with NEON floating-point extension includes: 32KB of instruction cache; 32KB of data cache; 256KB of L2 cache; and 64KB of RAM.

The rich peripheral set provides the ability to control external peripheral devices and communicate with external processors. For details on each peripheral, see the related sections in this document and the associated peripheral reference guides. The peripheral set includes: HD video processing subsystem (HDVPSS), which provides output of simultaneous HD and SD analog video and dual HD video inputs; up to two Gigabit Ethernet MACs (10 Mbps,100, Mbps, 1000 Mbps) with GMII and MDIO interface; two USB ports with integrated 2.0 PHY; PCIe port x2 lanes GEN2 compliant interface, which allows the device to act as a PCIe root complex or device endpoint; one 6-channel McASP audio serial port (with DIT mode); two dual-channel McASP audio serial ports (with DIT mode); one McBSP multichannel buffered serial port; three UARTs with IrDA and CIR support; SPI serial interface; SD and SDIO serial interface; two I2C master and slave interfaces; up to 64 GPIO pins; seven 32-bit timers; system watchdog timer; dual DDR2 and DDR3 SDRAM interface; flexible 8-bit and 16-bit asynchronous memory interface; and up to two SATA interfaces for external storage on two disk drives or more with the use of a port multiplier.

The device also includes an SGX530 3D graphics engine (available only on the AM3894 device) to off-load many video and imaging processing tasks from the core. Additionally, the device has a complete set of development tools for the ARM, including C compilers and a Microsoft Windows debugger interface for visibility into source code execution.

The device package has been specially engineered with Via Channel technology. This technology allows use of 0.8-mm pitch PCB feature sizes in this 0.65-mm pitch package, and substantially reduces PCB costs. Via Channel technology also allows PCB routing in only two signal layers due to the increased layer efficiency of the Via Channel BGA technology.
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技術資料

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上位の文書 タイプ タイトル フォーマットオプション 最新の英語版をダウンロード 日付
* データシート AM389x Sitara ARM Microprocessors (MPUs) データシート (Rev. G) PDF | HTML 2015年 3月 17日
* エラッタ AM389x Sitara ARM Microprocessors Silicon Errata (Rev 2.1 & Earlier) (Rev. H) 2015年 3月 17日
* ユーザー・ガイド AM389x Sitara ARM Microprocessors (MPUs) Technical Reference Manual (Rev. C) 2015年 3月 19日
アプリケーション・ノート High-Speed Interface Layout Guidelines (Rev. J) PDF | HTML 2023年 2月 24日
その他の技術資料 From Start to Finish: A Product Development Roadmap for Sitara™ Processors 2020年 12月 16日
ユーザー・ガイド How-To and Troubleshooting Guide for PRU-ICSS PROFIBUS 2018年 9月 24日
アプリケーション・ノート 0.65 mm Pitch Flip Chip Ball Grid Array Package Reference Guide (Rev. B) PDF | HTML 2015年 12月 1日
アプリケーション・ノート DM816xx Easy CYG Package PCB Escape Routing (Rev. A) 2015年 3月 19日
アプリケーション・ノート TMS320DM816x/TMS320C6A816x/AM389x Power Estimation Spreadsheet 2011年 5月 18日
アプリケーション・ノート PCIe to USB on the TMS320DM816x/TMS320C6A816x/AM389x Evaluation Board 2011年 3月 1日
アプリケーション・ノート TMS320DM816x/C6A816x/AM389x DDR3 Initialization With Software Leveling 2011年 3月 1日

設計と開発

その他のアイテムや必要なリソースを参照するには、以下のタイトルをクリックして詳細ページをご覧ください。

デバッグ・プローブ

TMDSEMU200-U — XDS200 USB デバッグ プローブ

XDS200 は、TI の組込みデバイスのデバッグに使用するデバッグ プローブ (エミュレータ) です。大半のデバイスでは、より新しく低コストな XDS110 (www.ti.com/tool/TMDSEMU110-U) の使用が推奨されます。XDS200 は、単一のポッドで IEEE1149.1、IEEE1149.7、SWD などの幅広い規格をサポートします。すべての XDS デバッグ プローブは、ETB (Embedded Trace Buffer、組込みトレース バッファ) 搭載のすべての Arm® と DSP プロセッサに対し、コア トレースとシステム トレースをサポートしています。

(...)

TI.com で取り扱いなし
デバッグ・プローブ

TMDSEMU560V2STM-U — XDS560™ ソフトウェア v2 システム・トレース USB デバッグ・プローブ

XDS560v2 は、XDS560™ ファミリのデバッグ・プローブの中で最高の性能を達成し、従来の JTAG 規格 (IEEE1149.1) と cJTAG (IEEE1149.7) の両方をサポートしています。シリアル・ワイヤ・デバッグ (SWD) をサポートしていないことに注意してください。

すべての XDS デバッグ・プローブは、組み込みトレース・バッファ (ETB) を搭載しているすべての ARM プロセッサと DSP プロセッサで、コア・トレースとシステム・トレースをサポートしています。ピン経由でコア・トレースを実行する場合、XDS560v2 PRO TRACE が必要です。

(...)

TI.com で取り扱いなし
デバッグ・プローブ

TMDSEMU560V2STM-UE — Spectrum Digital XDS560v2 システム・トレース USB およびイーサネット

The XDS560v2 System Trace is the first model of the XDS560v2 family of high-performance debug probes (emulators) for TI processors. The XDS560v2 is the highest performance of the XDS family of debug probes and supports both the traditional JTAG standard (IEEE1149.1) and cJTAG (IEEE1149.7).

The (...)

TI.com で取り扱いなし
ソフトウェア開発キット (SDK)

LINUXEZSDK-AM389X-AM387X — AM3871、AM3872、AM3874、AM3894、AM3892 向け Linux EZ SDK - ALPHA

SITARA LINUX SDK

Linux Software Development Kits (SDK) provide Sitara™ developers with an easy set up and quick out-of-box experience that is specific to and highlights the features of TI's ARM processors. Launching demos, benchmarks and applications is a snap with the included graphical user (...)

サポート対象の製品とハードウェア

サポート対象の製品とハードウェア
ダウンロードオプション
ソフトウェア開発キット (SDK)

LINUXSDK-AM17X — Linux SDK、AM1707 / AM1705 用

SITARA LINUX SDK

Linux Software Development Kits (SDK) provide Sitara™ developers with an easy set up and quick out-of-box experience that is specific to and highlights the features of TI's ARM processors. Launching demos, benchmarks and applications is a snap with the included graphical user (...)

サポート対象の製品とハードウェア

サポート対象の製品とハードウェア
ダウンロードオプション
IDE (統合開発環境)、コンパイラ、またはデバッガ

CCSTUDIO — Code Composer Studio 統合開発環境（IDE）

Code Composer Studio is an integrated development environment (IDE) for TI's microcontrollers and processors. It is comprised of a rich suite of tools used to build, debug, analyze and optimize embedded applications. Code Composer Studio is available across Windows®, Linux® and macOS® platforms.

(...)

サポート対象の製品とハードウェア

サポート対象の製品とハードウェア
開始 ダウンロードオプション
ソフトウェア・プログラミング・ツール

UNIFLASH — ほとんどの TI 製マイコン（MCU）とミリ波センサに対応する UniFlash

UniFlash is a software tool for programming on-chip flash on TI microcontrollers and wireless connectivity devices and on-board flash for TI processors. UniFlash provides both graphical and command-line interfaces.

UniFlash can be run from the cloud on the TI Developer Zone or downloaded and used (...)

サポート対象の製品とハードウェア

サポート対象の製品とハードウェア
開始 ダウンロードオプション
シミュレーション・モデル

AM389x CYG BSDL Model

SPRM514.ZIP (19 KB) - BSDL Model
ダウンロード
計算ツール

CLOCKTREETOOL — Clock Tree Tool for Sitara™ ARM® Processors

The Clock Tree Tool (CTT) for Sitara™ ARM®, Automotive, and Digital Signal Processors is an interactive clock tree configuration software that provides information about the clocks and modules in these TI devices. It allows the user to:
  • Visualize the device clock tree
  • Interact with clock tree (...)
ユーザー ガイド: PDF
View Options
パッケージ ピン数 CAD シンボル、フットプリント、および 3D モデル
FCBGA (CYG) 1031 Ultra Librarian
TI の評価基板に関する標準契約約款が適用されます。

購入と品質

記載されている情報：
  • RoHS
  • REACH
  • デバイスのマーキング
  • リード端子の仕上げ / ボールの原材料
  • MSL 定格 / ピーク リフロー
  • MTBF/FIT 推定値
  • 使用材料
  • 認定試験結果
  • 継続的な信頼性モニタ試験結果
記載されている情報：
  • ファブ拠点
  • アセンブリ拠点

サポートとトレーニング

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