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SM320F2812-EP

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具有 150MHz 频率、256KB 闪存、EMIF 的 C2000™ 增强型产品 32 位 MCU

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SM320F2812-EP

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CPU 1 C28 Frequency (MHz) 150 Flash memory (kByte) 256 RAM (kByte) 36 ADC type 12-bit Total processing (MIPS) 150 Features 2-pin oscillator, 32-bit CPU timers, External memory interface, McBSP, Watchdog timer UART 2 CAN (#) 1 Sigma-delta filter 0 PWM (Ch) 16 Security Secure storage Number of ADC channels 16 Direct memory access (Ch) 0 SPI 1 QEP 2 USB No Hardware accelerators CPU only Edge AI enabled Yes Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product Communication interface CAN, McBSP, SPI, UART Operating system BareMetal (No OS), FreeRTOS, SafeRTOS Nonvolatile memory (kByte) 256 Number of GPIOs 56
CPU 1 C28 Frequency (MHz) 150 Flash memory (kByte) 256 RAM (kByte) 36 ADC type 12-bit Total processing (MIPS) 150 Features 2-pin oscillator, 32-bit CPU timers, External memory interface, McBSP, Watchdog timer UART 2 CAN (#) 1 Sigma-delta filter 0 PWM (Ch) 16 Security Secure storage Number of ADC channels 16 Direct memory access (Ch) 0 SPI 1 QEP 2 USB No Hardware accelerators CPU only Edge AI enabled Yes Operating temperature range (°C) -55 to 125 Rating HiRel Enhanced Product Communication interface CAN, McBSP, SPI, UART Operating system BareMetal (No OS), FreeRTOS, SafeRTOS Nonvolatile memory (kByte) 256 Number of GPIOs 56
LQFP (PGF) 176 676 mm² (26 mm × 26 mm)
  • Controlled Baseline
    • One Assembly/Test/Fabrication Site
  • Extended Temperature Performance of –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • High-Performance Static CMOS Technology
    • 150 MHz (6.67-ns Cycle Time)
    • Low-Power (1.8-V Core @135 MHz, 1.9-V Core @150 MHz, 3.3-V I/O) Design
  • JTAG Boundary Scan Support(2)
  • High-Performance 32-Bit CPU (320C28x)
    • 16 × 16 and 32 × 32 MAC Operations
    • 16 × 16 Dual MAC
    • Harvard Bus Architecture
    • Atomic Operations
    • Fast Interrupt Response and Processing
    • Unified Memory Programming Model
    • 4M Linear Program/Data Address Reach
    • Code-Efficient (in C/C++ and Assembly)
    • 320F24x/LF240x Processor Source Code Compatible
  • On-Chip Memory
    • Flash Devices: Up to 128K × 16 Flash
      (Four 8K × 16 and Six 16K × 16 Sectors)
    • ROM Devices: Up to 128K × 16 ROM
    • 1K × 16 OTP ROM
    • L0 and L1: 2 Blocks of 4K × 16 Each Single-Access RAM (SARAM)
    • H0: 1 Block of 8K × 16 SARAM
    • M0 and M1: 2 Blocks of 1K × 16 Each SARAM
  • Boot ROM (4K × 16)
    • With Software Boot Modes
    • Standard Math Tables
  • External Interface (2812)
    • Over 1M × 16 Total Memory
    • Programmable Wait States
    • Programmable Read/Write Strobe Timing
    • Three Individual Chip Selects
  • Clock and System Control
    • Dynamic PLL Ratio Changes Supported
    • On-Chip Oscillator
    • Watchdog Timer Module
  • Three External Interrupts
  • Peripheral Interrupt Expansion (PIE) Block
    That Supports 45 Peripheral Interrupts
  • Three 32-Bit CPU-Timers
  • 128-Bit Security Key/Lock
    • Protects Flash/ROM/OTP and L0/L1 SARAM
    • Prevents Firmware Reverse Engineering
  • Motor Control Peripherals
    • Two Event Managers (EVA, EVB)
    • Compatible to 240xA Devices
  • Serial Port Peripherals
    • Serial Peripheral Interface (SPI)
    • Two Serial Communications Interfaces (SCIs), Standard UART
    • Enhanced Controller Area Network (eCAN)
    • Multichannel Buffered Serial Port (McBSP)
  • 12-Bit ADC, 16 Channels
    • 2 × 8 Channel Input Multiplexer
    • Two Sample-and-Hold
    • Single/Simultaneous Conversions
    • Fast Conversion Rate: 80 ns/12.5 MSPS
  • Up to 56 General Purpose I/O (GPIO) Pins
  • Advanced Emulation Features
    • Analysis and Breakpoint Functions
    • Real-Time Debug via Hardware
  • Development Tools Include
    • ANSI C/C++ Compiler/Assembler/Linker
    • Code Composer Studio™ IDE
    • DSP/BIOS™
  • Low-Power Modes and Power Savings
    • IDLE, STANDBY, HALT Modes Supported
    • Disable Individual Peripheral Clocks
  • Package Options
    • 179-Ball MicroStar BGA™ (GHH), (2812)
    • 176-Pin Low-Profile Quad Flatpack (LQFP) (PGF) (2812)

TMS320C24x, Code Composer Studio, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments.
(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
(2) IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port
  • Controlled Baseline
    • One Assembly/Test/Fabrication Site
  • Extended Temperature Performance of –55°C to 125°C
  • Enhanced Diminishing Manufacturing Sources (DMS) Support
  • Enhanced Product-Change Notification
  • Qualification Pedigree(1)
  • High-Performance Static CMOS Technology
    • 150 MHz (6.67-ns Cycle Time)
    • Low-Power (1.8-V Core @135 MHz, 1.9-V Core @150 MHz, 3.3-V I/O) Design
  • JTAG Boundary Scan Support(2)
  • High-Performance 32-Bit CPU (320C28x)
    • 16 × 16 and 32 × 32 MAC Operations
    • 16 × 16 Dual MAC
    • Harvard Bus Architecture
    • Atomic Operations
    • Fast Interrupt Response and Processing
    • Unified Memory Programming Model
    • 4M Linear Program/Data Address Reach
    • Code-Efficient (in C/C++ and Assembly)
    • 320F24x/LF240x Processor Source Code Compatible
  • On-Chip Memory
    • Flash Devices: Up to 128K × 16 Flash
      (Four 8K × 16 and Six 16K × 16 Sectors)
    • ROM Devices: Up to 128K × 16 ROM
    • 1K × 16 OTP ROM
    • L0 and L1: 2 Blocks of 4K × 16 Each Single-Access RAM (SARAM)
    • H0: 1 Block of 8K × 16 SARAM
    • M0 and M1: 2 Blocks of 1K × 16 Each SARAM
  • Boot ROM (4K × 16)
    • With Software Boot Modes
    • Standard Math Tables
  • External Interface (2812)
    • Over 1M × 16 Total Memory
    • Programmable Wait States
    • Programmable Read/Write Strobe Timing
    • Three Individual Chip Selects
  • Clock and System Control
    • Dynamic PLL Ratio Changes Supported
    • On-Chip Oscillator
    • Watchdog Timer Module
  • Three External Interrupts
  • Peripheral Interrupt Expansion (PIE) Block
    That Supports 45 Peripheral Interrupts
  • Three 32-Bit CPU-Timers
  • 128-Bit Security Key/Lock
    • Protects Flash/ROM/OTP and L0/L1 SARAM
    • Prevents Firmware Reverse Engineering
  • Motor Control Peripherals
    • Two Event Managers (EVA, EVB)
    • Compatible to 240xA Devices
  • Serial Port Peripherals
    • Serial Peripheral Interface (SPI)
    • Two Serial Communications Interfaces (SCIs), Standard UART
    • Enhanced Controller Area Network (eCAN)
    • Multichannel Buffered Serial Port (McBSP)
  • 12-Bit ADC, 16 Channels
    • 2 × 8 Channel Input Multiplexer
    • Two Sample-and-Hold
    • Single/Simultaneous Conversions
    • Fast Conversion Rate: 80 ns/12.5 MSPS
  • Up to 56 General Purpose I/O (GPIO) Pins
  • Advanced Emulation Features
    • Analysis and Breakpoint Functions
    • Real-Time Debug via Hardware
  • Development Tools Include
    • ANSI C/C++ Compiler/Assembler/Linker
    • Code Composer Studio™ IDE
    • DSP/BIOS™
  • Low-Power Modes and Power Savings
    • IDLE, STANDBY, HALT Modes Supported
    • Disable Individual Peripheral Clocks
  • Package Options
    • 179-Ball MicroStar BGA™ (GHH), (2812)
    • 176-Pin Low-Profile Quad Flatpack (LQFP) (PGF) (2812)

TMS320C24x, Code Composer Studio, DSP/BIOS, and MicroStar BGA are trademarks of Texas Instruments.
(1) Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits.
(2) IEEE Standard 1149.1-1990, IEEE Standard Test-Access Port

The SM320F2810-EP, SM320F2811-EP, SM320F2812-EP, SM320C2810-EP, SM320C2811-EP, and SM320C2812-EP devices, members of the TMS320C28x™ DSP generation, are highly integrated, high-performance solutions for demanding control applications. The functional blocks and the memory maps are described in Section 3, Functional Overview.

Throughout this document, SM320F2810-EP, SM320F2811-EP, and SM320F2812-EP are abbreviated as F2810, F2811, and F2812, respectively. F281x denotes all three Flash devices. SM320C2810-EP, SM320C2811-EP, and SM320C2812-EP are abbreviated as C2810, C2811, and C2812, respectively. C281x denotes all three ROM devices. 2810 denotes both F2810 and C2810 devices; 2811 denotes both F2811 and C2811 devices; and 2812 denotes both F2812 and C2812 devices.

The SM320F2810-EP, SM320F2811-EP, SM320F2812-EP, SM320C2810-EP, SM320C2811-EP, and SM320C2812-EP devices, members of the TMS320C28x™ DSP generation, are highly integrated, high-performance solutions for demanding control applications. The functional blocks and the memory maps are described in Section 3, Functional Overview.

Throughout this document, SM320F2810-EP, SM320F2811-EP, and SM320F2812-EP are abbreviated as F2810, F2811, and F2812, respectively. F281x denotes all three Flash devices. SM320C2810-EP, SM320C2811-EP, and SM320C2812-EP are abbreviated as C2810, C2811, and C2812, respectively. C281x denotes all three ROM devices. 2810 denotes both F2810 and C2810 devices; 2811 denotes both F2811 and C2811 devices; and 2812 denotes both F2812 and C2812 devices.
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技术文档

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顶层文档 类型 标题 格式选项 下载最新的英语版本 日期
* 数据表 Digital Signal Processors. 数据表 (Rev. B) 2010-4-20
* 勘误表 TMS320F281x DSPs Silicon Errata (Rev. T) PDF | HTML 2023-12-19
* 辐射与可靠性报告 SM320F2812PGFMEP Reliability Report 2011-8-26
* VID SM320F2812-EP VID V6205601 2016-6-21
应用手册 Programming TMS320x28xx and 28xxx Peripherals in C/C++ (Rev. E) PDF | HTML 2017-12-19

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XDS200 通过 TI 20 引脚连接器（带有适用于 TI 14 引脚、Arm Cortex® 10 引脚和 Arm 20 引脚的多个适配器）连接到目标板，并通过 USB2.0 高速 (...)

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对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS 调试探针均支持核心和系统跟踪。  对于引脚上的跟踪，则需要使用 XDS560v2 PRO TRACE。

XDS560v2 通过 MIPI HSPT 60 引脚连接器（带有多个用于 TI 14 引脚、TI 20 引脚和 ARM 20 引脚的适配器）连接到目标板，并通过 USB2.0 高速 (...)

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XDS560v2 System Trace 在其巨大的外部存储器缓冲区中加入了系统引脚跟踪。这种外部存储器缓冲区适用于指定的 TI 器件，通过捕获相关器件级信息，获得准确的总线性能活动和吞吐量，并对内核和外设进行电源管理。此外，对于带有嵌入式缓冲跟踪器 (ETB) 的所有 ARM 和 DSP 处理器，所有 XDS (...)

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来源：Shanghai Uni-Sentry Intelligent Technology Co., LTD
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USIT-3P-SECIC-PQC — Uni-Sentry SecIC-PQC 算法固件

Uni-Sentry 的安全解决方案采用 PQC 算法，能够抵御量子计算机对传统加密算法构成的解密威胁。PQC 固件与硬件安全模块 (HSM) 进行了协同优化，利用硬件加速和安全增强功能来提高加密算法执行效率和安全性。 


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  • SP 800-208：LMS 和 XMSS
  • FIPS 203 (ML-KEM)： CRYSTALS-KYBER 
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UNIFLASH — UniFlash for most TI microcontrollers (MCUs) and mmWave sensors

UniFlash 是 TI 庞大的 CCStudio™ 开发生态系统的成员并且是一款软件工具，用于对 TI 微控制器和无线连接器件上的片上闪存以及 TI 处理器的板载闪存进行编程。UniFlash 提供图形界面和命令行界面，可在桌面上或云中运行。

可以在 CCStudio™ 开发人员专区从云中运行 UniFlash，也可以将其下载并在 Windows®、Linux® 和 macOS® 计算机上使用。

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SPRC125 — Download TMS320F2810, TMS320F2811 and TMS320F2812 Flash API

Are you looking to integrate flash programming into your project?

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TI 与多家公司携手推出适用于 TI C2000 器件的各种解决方案和服务。这些公司可使用 C2000 器件加速您的量产流程。下载此搜索工具，快速浏览第三方详细信息，并寻找合适的第三方来满足您的需求。

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