Product details

Sample rate (max) (Msps) 500 Resolution (Bits) 12 Number of input channels 2 Interface type DDR LVDS Analog input BW (MHz) 1000 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1 Power consumption (typ) (mW) 1350 Architecture Pipeline SNR (dB) 63.8 ENOB (Bits) 10.3 SFDR (dB) 77 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 500 Resolution (Bits) 12 Number of input channels 2 Interface type DDR LVDS Analog input BW (MHz) 1000 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 1 Power consumption (typ) (mW) 1350 Architecture Pipeline SNR (dB) 63.8 ENOB (Bits) 10.3 SFDR (dB) 77 Operating temperature range (°C) -40 to 85 Input buffer No
NFBGA (ZAY) 196 144 mm² 12 x 12
  • Dual Channel
  • 12-Bit Resolution
  • Maximum Clock Rate: 500 Msps
  • Low Swing Fullscale Input: 1.25 Vpp
  • Analog Input Buffer with High Impedance Input
  • Input Bandwidth (3dB): >1.0 GHz
  • Data Output Interface: DDR LVDS
  • Optional 2x Decimation with Low Pass or
    High Pass Filter
  • 196-Pin BGA Package (12 × 12mm)
  • Dual Channel
  • 12-Bit Resolution
  • Maximum Clock Rate: 500 Msps
  • Low Swing Fullscale Input: 1.25 Vpp
  • Analog Input Buffer with High Impedance Input
  • Input Bandwidth (3dB): >1.0 GHz
  • Data Output Interface: DDR LVDS
  • Optional 2x Decimation with Low Pass or
    High Pass Filter
  • 196-Pin BGA Package (12 × 12mm)

The ADS5407 is a high linearity dual channel 12-bit, 500 MSPS analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip track-and-hold from disturbing the signal source as well as providing a high-impedance input. Optionally the output data can be decimated by two. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196 pin BGA package and is specified over the full industrial temperature range (–40°C to 85°C).

The ADS5407 is a high linearity dual channel 12-bit, 500 MSPS analog-to-digital converter (ADC) easing front end filter design for wide bandwidth receivers. The analog input buffer isolates the internal switching of the on-chip track-and-hold from disturbing the signal source as well as providing a high-impedance input. Optionally the output data can be decimated by two. Designed for high SFDR, the ADC has low-noise performance and outstanding spurious-free dynamic range over a large input-frequency range. The device is available in a 196 pin BGA package and is specified over the full industrial temperature range (–40°C to 85°C).

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Technical documentation

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* Data sheet Dual Channel 12-Bit 500 Msps Analog to Digital Converter datasheet (Rev. B) 08 Jan 2014
More literature Comparing Power-Supply Architectures for a 12-bit ADC 25 Jul 2017
Technical article Do you always need a LDO in front of your data converter? PDF | HTML 22 Dec 2016
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013

Design & development

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Design tool

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Using a switch mode power supply (SMPS) instead, such as the (...)

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NFBGA (ZAY) 196 Ultra Librarian

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