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High-speed ADCs (≥10 MSPS)

ADS62C15

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Dual-Channel, 11-Bit, 125-MSPS Analog-to-Digital Converter (ADC)

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Data sheet

ADS62C15

ACTIVE
Data sheet Order now

Product details

Sample rate (max) (Msps) 125 Resolution (Bits) 11 Number of input channels 2 Interface type Serial LVDS Analog input BW (MHz) 450 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 740 Architecture Pipeline SNR (dB) 67.2 ENOB (Bits) 10.8 SFDR (dB) 89 Operating temperature range (°C) -40 to 85 Input buffer No
Sample rate (max) (Msps) 125 Resolution (Bits) 11 Number of input channels 2 Interface type Serial LVDS Analog input BW (MHz) 450 Features High Performance Rating Catalog Peak-to-peak input voltage range (V) 2 Power consumption (typ) (mW) 740 Architecture Pipeline SNR (dB) 67.2 ENOB (Bits) 10.8 SFDR (dB) 89 Operating temperature range (°C) -40 to 85 Input buffer No
VQFN (RGC) 64 81 mm² 9 x 9
  • Maximum Sample Rate: 125 MSPS
  • 11-Bit Resolution With No Missing Codes
  • 82 dBc SFDR at Fin = 117 MHz
  • 67 dBFS SNR at Fin = 117 MHz
  • 77.5 dBFS SNR at Fin = 117 MHz, 20MHz bandwidth
    using technology
  • 92 dB Crosstalk
  • Parallel CMOS and DDR LVDS Output Options
  • 3.5 dB Coarse Gain and Programmable Fine Gain
    up to 6 dB for SNR/SFDR Trade-Off
  • Digital Processing Block With:
    • Offset Correction
    • Fine Gain Correction, in Steps of 0.05 dB
    • Decimation by 2/4/8
    • Built-in and Custom Programmable 24-Tap Low/High/
      Band Pass Filters
  • Supports Sine, LVPECL, LVDS and LVCMOS Clocks and
    Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference; Also Supports External Reference
  • 64-QFN Package (9mm × 9mm)
  • Maximum Sample Rate: 125 MSPS
  • 11-Bit Resolution With No Missing Codes
  • 82 dBc SFDR at Fin = 117 MHz
  • 67 dBFS SNR at Fin = 117 MHz
  • 77.5 dBFS SNR at Fin = 117 MHz, 20MHz bandwidth
    using technology
  • 92 dB Crosstalk
  • Parallel CMOS and DDR LVDS Output Options
  • 3.5 dB Coarse Gain and Programmable Fine Gain
    up to 6 dB for SNR/SFDR Trade-Off
  • Digital Processing Block With:
    • Offset Correction
    • Fine Gain Correction, in Steps of 0.05 dB
    • Decimation by 2/4/8
    • Built-in and Custom Programmable 24-Tap Low/High/
      Band Pass Filters
  • Supports Sine, LVPECL, LVDS and LVCMOS Clocks and
    Amplitude Down to 400 mVPP
  • Clock Duty Cycle Stabilizer
  • Internal Reference; Also Supports External Reference
  • 64-QFN Package (9mm × 9mm)

ADS62C15 is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62C15 uses proprietary technology that can be used to overcome SNR limitation due to quantization noise (for bandwidths less than Nyquist, Fs/2). It includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62C15 includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. The device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).

ADS62C15 is a dual channel 11-bit A/D converter with maximum sample rates up to 125 MSPS. It combines high performance and low power consumption in a compact 64 QFN package. Using an internal sample and hold and low jitter clock buffer, the ADC supports high SNR and high SFDR at high input frequencies. It has coarse and fine gain options that can be used to improve SFDR performance at lower full-scale input ranges.

ADS62C15 uses proprietary technology that can be used to overcome SNR limitation due to quantization noise (for bandwidths less than Nyquist, Fs/2). It includes a digital processing block that consists of several useful and commonly used digital functions such as ADC offset correction, fine gain correction (in steps of 0.05 dB), decimation by 2,4,8 and in-built and custom programmable filters. By default, the digital processing block is bypassed, and its functions are disabled.

Two output interface options exist – parallel CMOS and DDR LVDS (Double Data Rate). ADS62C15 includes internal references while traditional reference pins and associated decoupling capacitors have been eliminated. The device can also be driven with an external reference. The device is specified over the industrial temperature range (–40°C to 85°C).
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Technical documentation

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Top documentation Type Title Format options Date
* Data sheet Dual Channel 11-Bits, 125MSPS ADC With Parallel CMOS/DDR LVDS Outputs datasheet (Rev. E) 09 Feb 2012
Application note Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A) 22 May 2015
Application note Why Use Oversampling when Undersampling Can Do the Job? (Rev. A) 19 Jul 2013
User guide TSW4200 Demonstration Kit User's Guide (Rev. C) 31 Oct 2012
Application note Band-Pass Filter Design Techniques for High-Speed ADCs 27 Feb 2012
Application note Understanding Low-Amplitude Behavior of 11-bit ADCs 22 Oct 2011
Application note Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A) 10 Sep 2010
Application note Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio 28 Apr 2009
User guide ADS62PxxEVM Quick Start Guide (Rev C Board) (Rev. A) 02 Apr 2009
Application note CDCE62005 as Clock Solution for High-Speed ADCs 04 Sep 2008
Application note CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters 08 Jun 2008
Application note Phase Noise Performance and Jitter Cleaning Ability of CDCE72010 02 Jun 2008
Application note QFN Layout Guidelines 28 Jul 2006

Design & development

For additional terms or required resources, click any title below to view the detail page where available.

GUI for evaluation module (EVM)

DATACONVERTERPRO-SW — High Speed Data Converter Pro GUI Installer, v5.31

This high-speed data converter pro GUI is a PC (Windows® XP/7/10 compatible) program designed to aid in evaluation of most TI high-speed data converter [analog-to-digital converter (ADC) and digital-to-analog converter (DAC)] and analog front-end (AFE) platforms. Designed to support the entire (...)

Supported products & hardware

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Support software

HSADC-SPI-UTILITY — ADS5400 EVM GUI

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Supported products & hardware
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Support software

SBAC120 — TIGAR Support Files

Supported products & hardware

Supported products & hardware
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Simulation model

ADS62Pxx Family TINA-TI Transient Reference Design

SBAM008.ZIP (6 KB) - TINA-TI Reference Design
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Simulation model

ADS62Pxx Family TINA-TI Transient Spice Model

SBAM007.TSM (14 KB) - TINA-TI Spice Model
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Simulation model

ADS62Pxx IBIS Model (Rev. A)

SLAC176A.ZIP (921 KB) - IBIS Model
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Calculation tool

ANALOG-ENGINEER-CALC — PC software analog engineer's calculator

The analog engineer’s calculator is designed to speed up many of the repetitive calculations that analog circuit design engineers use on a regular basis. This PC-based tool provides a graphical interface with a list of various common calculations ranging from setting operational-amplifier (...)

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Supported products & hardware
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Design tool

SBAC119 — TIGAR (Texas Instruments Graphical Evaluation of ADC Response Tool)

Supported products & hardware

Supported products & hardware
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Simulation tool

PSPICE-FOR-TI — PSpice® for TI design and simulation tool

PSpice® for TI is a design and simulation environment that helps evaluate functionality of analog circuits. This full-featured, design and simulation suite uses an analog analysis engine from Cadence®. Available at no cost, PSpice for TI includes one of the largest model libraries in the (...)
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